MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 364

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Programmable Interrupt Timers (PIT0–PIT3)
19-4
15–12
DOZE
Field
11–8
OVW
DBG
PRE
PIE
PIF
7
6
5
4
3
2
Reserved, must be cleared.
Prescaler. The read/write prescaler bits select the internal bus clock divisor to generate the PIT clock. To accurately
predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing
PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the
prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN
bit stops the prescaler counter.
Reserved, must be cleared.
Doze Mode Bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset clears DOZE.
0 PIT function not affected in doze mode
1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in
Debug mode bit. Controls the function of PIT in halted/debug mode. Reset clears DBG. During debug mode, register
read and write accesses function normally. When debug mode is exited, timer operation continues from the state it
was in before entering debug mode, but any updates made in debug mode remain.
0 PIT function not affected in debug mode
1 PIT function stopped in debug mode
Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the DBG bit
Overwrite. Enables writing to PMRn to immediately overwrite the value in the PIT counter.
0 Value in PMRn replaces value in PIT counter when count reaches 0x0000.
1 Writing PMRn immediately replaces value in PIT counter.
PIT interrupt enable. This read/write bit enables PIF flag to generate interrupt requests.
0 PIF interrupt requests disabled
1 PIF interrupt requests enabled
PIT interrupt flag. This read/write bit is set when PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by
writing to PMR. Writing 0 has no effect. Reset clears PIF.
0 PIT count has not reached 0x0000.
1 PIT count has reached 0x0000.
before entering doze mode.
from 0 to 1 during debug mode stops the PIT timer.
Table 19-3. PCSRn Field Descriptions
0000
0001
0010
1101
1110
1111
PRE
...
Internal Bus Clock
Divisor
2
2
2
Description
2
2
2
...
13
14
15
0
1
2
Equivalent
Decimal
16384
32768
8192
...
1
2
4
Freescale Semiconductor