MCF5282CVM66 Freescale, MCF5282CVM66 Datasheet - Page 547

• Manufacturer Part Number: MCF5282CVM66
• Manufacturer: Freescale

Specifications of MCF5282CVM66

• Cpu Family: MCF528x
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 66MHz
• Interface Type: CAN/I2C/QSPI/UART
• Total Internal Ram Size: 64KB
• # I/os (max): 150
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 3.3V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: MA-BGA
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Note: The reset value for these fields is the current signal state if DDR is an input; otherwise, they are undefined.
28.6.4
DDRQA and DDRQB are associated with port QA and QB digital I/O signals. Setting a bit in these
registers configures the corresponding signal as an output. Clearing a bit in these registers configures the
corresponding signal as an input. During QADC initialization, port QA and QB signals that will be used
as direct or multiplexed analog inputs must have their corresponding data direction register bits cleared.
When a port QA or QB signal that is programmed as an output is selected for analog conversion, the
voltage sampled is that of the output digital driver as influenced by the load.
When the MUX (externally multiplexed) bit is set in QACR0, the data direction register settings are
ignored for the bits corresponding to PQA[1:0], and the two multiplexed address (MA[1:0]) output signals.
The MA[1:0] signals are forced to be digital outputs, regardless of their data direction setting, and the
multiplexed address outputs are driven. The data returned during a port data register read is the value of
the MA[1:0] signals, regardless of their data direction setting.
Similarly, when the external trigger signals are assigned to port signals and external trigger queue
operating mode is selected, the data direction setting for the corresponding signals, PQA3 and/or PQA4,
is ignored. The port signals are forced to be digital inputs for ETRIG1 and/or ETRIG2. The data returned
during a port data register read is the value of the ETRIG[2:1] signals, regardless of their data direction
setting.
Freescale Semiconductor
Address
Address
Reset
Reset
R/W:
R/W:
Field
Field
Port QA and QB Data Direction Register (DDRQA & DDRQB)
Use caution when mixing digital and analog inputs. They should be isolated
as much as possible. Rise and fall times should be as large as possible to
minimize ac coupling effects.
7
7
Figure 28-6. QADC Port QA Data Direction Register (DDRQA)
Figure 28-5. QADC Port QB Data Register (PORTQB)
—
R
6
6
0000
—
R
5
5
IPSBAR + 0x19_0007
IPSBAR + 0x19_0008
DDQA4
NOTE
4
4
0000_0000
R/W
DDQA3
PQB3
(AN3)
(ANZ)
3
3
PQB2
(ANY)
(AN2)
Queued Analog-to-Digital Converter (QADC)
—
R
2
2
See Note
R/W
DDQA1
PQA1
(ANX)
(AN1)
1
1
R/W
DDQA0
(ANW)
PQA0
(AN0)
0
0
28-9