MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 964

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.7.4
Port E is associated with the external bus control outputs R/W, LSTRB, LDS and RE, the free-running
clock outputs ECLK and ECLK2X, as well as with the TAGHI, TAGLO, MODA and MODB and
interrupt inputs IRQ and XIRQ.
Port E pins PE[7:2] can be used for either general-purpose I/O or with the alternative functions.
Port E pin PE[7] an be used for either general-purpose I/O or as the free-running clock ECLKX2 output
running at the core clock rate. The clock output is always enabled in emulation modes.
Port E pin PE[4] an be used for either general-purpose I/O or as the free-running clock ECLK output
running at the bus clock rate or at the programmed divided clock rate. The clock output is always enabled
in emulation modes.
Port E pin PE[1] can be used for either general-purpose input or as the level- or falling edge-sensitive IRQ
interrupt input. IRQ will be enabled by setting the IRQEN configuration bit
Control Register
reset so this pin is initially configured as a simple input with a pull-up.
Port E pin PE[0] can be used for either general-purpose input or as the level-sensitive XIRQ interrupt
input. XIRQ can be enabled by clearing the X-bit in the CPU’s condition code register. It is inhibited at
reset so this pin is initially configured as a high-impedance input with a pull-up.
Port E pins PE[5] and PE[6] are configured for reduced input threshold in certain modes (refer to
S12X_EBI section).
23.0.7.5
Port K pins PK[7:0] can be used for either general-purpose I/O, or, in 144-pin packages, also with the
external bus interface. In this case port K pins PK[6:0] are associated with the external address bus outputs
ADDR22–ADDR16 and PK7 is associated to the EWAIT input.
Port K pin PE[7] is configured for reduced input threshold in certain modes (refer to S12X_EBI section).
23.0.7.6
This port is associated with the ECT module. Port T pins PT[7:0] can be used for either general-purpose
I/O, or with the channels of the enhanced capture timer.
23.0.7.7
This port is associated with SCI0, SCI1 and SPI0. Port S pins PS[7:0] can be used either for general-
purpose I/O, or with the SCI and SPI subsystems.
The SPI0 pins can be re-routed. Refer to
966
Port E
Port K
Port T
Port S
Port K is not available in 80-pin packages. PK[6] is not available in 112-pin
packages.
(IRQCR)”) and clearing the I-bit in the CPU’s condition code register. It is inhibited at
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 23.0.5.37, “Module Routing Register
NOTE
(Section 23.0.5.14, “IRQ
Freescale Semiconductor
(MODRR)”.