MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 723

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

19.4.5.3.1
The format of the control information byte for both CPU and XGATE modules is dependent upon the
active trace mode and tracing source as described below. In normal mode or loop1 mode, tracing of
XGATE activity XINF is used to store control information. In normal mode or loop1 mode, tracing of CPU
activity CINF is used to store control information. In detail mode, CXINF contains the control information.
Freescale Semiconductor
Field
Field
XSD
CSD
XDV
CDV
7
4
7
4
Bit 7
Bit 7
CSD
XSD
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or
destination address. This is only used in normal and loop1 mode tracing.
0 Source Address
1 Destination Address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in normal and loop1 mode, to indicate that the XGATE trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or
destination address. This is only used in normal and loop1 mode tracing.
0 Source Address
1 Destination Address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in normal and loop1 mode, to indicate that the CPU trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
Information Byte Organization
Bit 6
Bit 6
0
0
Figure 19-24. XGATE Information Byte XINF
Figure 19-25. CPU Information Byte CINF
Bit 5
Bit 5
Table 19-40. XINF Field Descriptions
Table 19-41. CINF Field Descriptions
0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
Bit 4
Bit 4
XDV
CDV
Description
Description
Bit 3
Bit 3
0
0
Bit 2
Bit 2
Chapter 19 S12X Debug (S12XDBGV2) Module
0
0
Bit 1
Bit 1
0
0
Bit 0
Bit 0
0
0
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