MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 1079

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

26.3.2.5
The EPROT register defines which EEPROM sectors are protected against program or erase operations.
During the reset sequence, the EPROT register is loaded from the EEPROM Protection byte at address
offset 0x0FFD (see
RNV[6:4] which are only readable. The EPOPEN and EPDIS bits can only be written to the protected
state. The EPS bits can be written anytime until bit EPDIS is cleared. If the EPOPEN bit is cleared, the
state of the EPDIS and EPS bits is irrelevant.
To change the EEPROM protection that will be loaded during the reset sequence, the EEPROM memory
must be unprotected, then the EEPROM Protection byte must be reprogrammed. Trying to alter data in any
protected area in the EEPROM memory will result in a protection violation error and the PVIOL flag will
be set in the ESTAT register. The mass erase of an EEPROM block is possible only when protection is
fully disabled by setting the EPOPEN and EPDIS bits.
Freescale Semiconductor
EPOPEN
RNV[6:4]
EPS[2:0]
Reset
EPDIS
Field
6–4
2–0
7
3
W
R
EPOPEN
Opens the EEPROM for Program or Erase
0 The entire EEPROM memory is protected from program and erase.
1 The EEPROM sectors not protected are enabled for program or erase.
Reserved Nonvolatile Bits — The RNV[6:4] bits should remain in the erased state “1” for future enhancements.
EEPROM Protection Address Range Disable — The EPDIS bit determines whether there is a protected area
in a specific region of the EEPROM memory ending with address offset 0x0FFF.
0 Protection enabled.
1 Protection disabled.
EEPROM Protection Address Size — The EPS[2:0] bits determine the size of the protected area as shown
inTable
EEPROM Protection Register (EPROT)
F
7
26-6. The EPS bits can only be written to while the EPDIS bit is set.
Table
= Unimplemented or Reserved
RNV6
F
26-1).All bits in the EPROT register are readable and writable except for
6
Figure 26-8. EEPROM Protection Register (EPROT)
Table 26-5. EPROT Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
RNV5
F
5
RNV4
F
4
Description
EPDIS
Chapter 26 4 Kbyte EEPROM Module (S12XEETX4KV2)
F
3
EPS2
F
2
EPS1
F
1
EPS0
F
0
1081