MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 433

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

1
2
10.3.2.7
The transmit buffer empty flags each have an associated interrupt enable bit in the CANTIER register.
Freescale Semiconductor
RSTATE[1:0]
TSTATE[1:0]
WUPIE and WUPE (see
mechanism from stop or wait is required.
Bus-off state is defined by the CAN standard (see Bosch CAN 2.0A/B protocol specification: for only transmitters. Because the
only possible state change for the transmitter from bus-off to TxOK also forces the receiver to skip its current state to RxOK,
the coding of the RXSTAT[1:0] flags define an additional bus-off state for the receiver (see
Flag Register
WUPIE
CSCIE
OVRIE
RXFIE
Field
5:4
3:2
7
6
1
0
1
Wake-Up Interrupt Enable
0 No interrupt request is generated from this event.
1 A wake-up event causes a Wake-Up interrupt request.
CAN Status Change Interrupt Enable
0 No interrupt request is generated from this event.
1 A CAN Status Change event causes an error interrupt request.
Receiver Status Change Enable — These RSTAT enable bits control the sensitivity level in which receiver state
changes are causing CSCIF interrupts. Independent of the chosen sensitivity level the RSTAT flags continue to
indicate the actual receiver state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by receiver state changes.
01 Generate CSCIF interrupt only if the receiver enters or leaves “bus-off” state. Discard other receiver state
10 Generate CSCIF interrupt only if the receiver enters or leaves “RxErr” or “bus-off”
11 Generate CSCIF interrupt on all state changes.
Transmitter Status Change Enable — These TSTAT enable bits control the sensitivity level in which transmitter
state changes are causing CSCIF interrupts. Independent of the chosen sensitivity level, the TSTAT flags
continue to indicate the actual transmitter state and are only updated if no CSCIF interrupt is pending.
00 Do not generate any CSCIF interrupt caused by transmitter state changes.
01 Generate CSCIF interrupt only if the transmitter enters or leaves “bus-off” state. Discard other transmitter
10 Generate CSCIF interrupt only if the transmitter enters or leaves “TxErr” or “bus-off” state. Discard other
11 Generate CSCIF interrupt on all state changes.
Overrun Interrupt Enable
0 No interrupt request is generated from this event.
1 An overrun event causes an error interrupt request.
Receiver Full Interrupt Enable
0 No interrupt request is generated from this event.
1 A receive buffer full (successful message reception) event causes a receiver interrupt request.
MSCAN Transmitter Flag Register (CANTFLG)
(CANRFLG)”).
changes for generating CSCIF interrupt.
receiver state changes for generating CSCIF interrupt.
state changes for generating CSCIF interrupt.
transmitter state changes for generating CSCIF interrupt.
Section 10.3.2.1, “MSCAN Control Register 0
Table 10-10. CANRIER Register Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
Description
(CANCTL0)”) must both be enabled if the recovery
Section 10.3.2.5, “MSCAN Receiver
2
state. Discard other
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