MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 659

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

18.3.2.2
Read: Anytime. In emulation modes read operations will return the data read from the external bus. In all
other modes the data are read from this register.
Write: Only if a transition is allowed (see
directed to the external bus.
The MODE bits of the MODE register are used to establish the MCU operating mode.
Freescale Semiconductor
Address: 0x000B PRR
1. External signal (see
Reset
MODC,
MODB,
MODA
Field
7–5
W
R
MODC
MODC
Mode Select Bits — These bits control the current operating mode during RESET high (inactive). The external
mode pins MODC, MODB, and MODA determine the operating mode during RESET low (active). The state of
the pins is latched into the respective register bits after the RESET signal goes inactive (see
Write restrictions exist to disallow transitions between certain modes.
changes. Attempting non authorized transitions will not change the MODE bits, but it will block further writes to
these register bits except in special modes.
Both transitions from normal single-chip mode to normal expanded mode and from emulation single-chip to
emulation expanded mode are only executed by writing a value of 3’b101 (write once). Writing any other value
will not change the MODE bits, but will block further writes to these register bits.
Changes of operating modes are not allowed when the device is secured, but it will block further writes to these
register bits except in special modes.
In emulation modes reading this address returns data from the external bus which has to be driven by the
emulator. It is therefore responsibility of the emulator hardware to provide the expected value (i.e. a value
corresponding to normal single chip mode while the device is in emulation single-chip mode or a value
corresponding to normal expanded mode while the device is in emulation expanded mode).
Mode Register (MODE)
7
XGATE write access to this register during an CPU access which makes use
of this register could lead to unexpected results.
1
Table
= Unimplemented or Reserved
MODB
MODB
18-2).
6
1
Table 18-7. MODE Field Descriptions
Figure 18-4. Mode Register (MODE)
MODA
MC9S12XDP512 Data Sheet, Rev. 2.21
MODA
5
1
Figure
CAUTION
18-5). In emulation modes write operations will be also
0
0
4
Description
0
0
3
Chapter 18 Memory Mapping Control (S12XMMCV3)
Figure 18-5
0
0
2
illustrates all allowed mode
0
0
1
Figure
18-5).
0
0
0
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