MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 472

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
When entering the power down mode, the MSCAN immediately stops all ongoing transmissions and
receptions, potentially causing CAN protocol violations. To protect the CAN bus system from fatal
consequences of violations to the above rule, the MSCAN immediately drives the TXCAN pin into a
recessive state.
In power down mode, all clocks are stopped and no registers can be accessed. If the MSCAN was not in
sleep mode before power down mode became active, the module performs an internal recovery cycle after
powering up. This causes some fixed delay before the module enters normal mode again.
10.4.5.7
The MSCAN can be programmed to wake up the MSCAN as soon as CAN bus activity is detected (see
control bit WUPE in
existing CAN bus action can be modified by applying a low-pass filter function to the RXCAN input line
while in sleep mode (see control bit WUPM in
(CANCTL1)”).
This feature can be used to protect the MSCAN from wake-up due to short glitches on the CAN bus lines.
Such glitches can result from—for example—electromagnetic interference within noisy environments.
10.4.6
The reset state of each individual bit is listed in
the registers and their bit-fields.
10.4.7
This section describes all interrupts originated by the MSCAN. It documents the enable bits and generated
flags. Each interrupt is listed and described separately.
10.4.7.1
The MSCAN supports four interrupt vectors (see
(for details see sections from
(CANRIER),” to
472
•
or
CPU is in wait mode and the CSWAI bit is set
Reset Initialization
Interrupts
Programmable Wake-Up Function
Description of Interrupt Operation
The user is responsible for ensuring that the MSCAN is not active when
power down mode is entered. The recommended procedure is to bring the
MSCAN into Sleep mode before the STOP or WAI instruction (if CSWAI
is set) is executed. Otherwise, the abort of an ongoing message can cause an
error condition and impact other CAN bus devices.
Section 10.3.2.8, “MSCAN Transmitter Interrupt Enable Register
Section 10.3.2.1, “MSCAN Control Register 0
Section 10.3.2.6, “MSCAN Receiver Interrupt Enable Register
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 10.3.2.2, “MSCAN Control Register 1
Section 10.3.2, “Register
NOTE
Table
10-37), any of which can be individually masked
(CANCTL0)”). The sensitivity to
Descriptions,” which details all
(CANTIER)”).
Freescale Semiconductor