MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 1265

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

A.5
This section summarizes the electrical characteristics of the various startup scenarios for oscillator and
phase-locked loop (PLL).
A.5.1
Table A-21
startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.
1
2
A.5.1.1
The release level V
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t
clock. The fastest startup time possible is given by n
A.5.1.2
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when V
the PORF bit in the CRG flags register has not been set.
A.5.1.3
When external reset is asserted for a time greater than PW
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.5.1.4
Out of stop the controller can be woken up by an external interrupt. A clock quality check as after POR is
performed before releasing the clocks to the system.
Freescale Semiconductor
Conditions are shown in
Num C
1 t
V
1
2
3
4
5
DD1
cycle
/V
D Reset input pulse width, minimum input time
D Startup from reset
D Interrupt pulse width, IRQ edge-sensitive mode
D Wait recovery startup time
D Fast wakeup from STOP
at 40Mhz Bus Clock
DD2
Reset, Oscillator, and PLL
summarizes several startup characteristics explained in this section. Detailed description of the
filter capacitors 220 nF, V
Startup
DD35
POR
SRAM Data Retention
External Reset
Stop Recovery
is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
PORR
Table
and the assert level V
CQOUT
A-4unless otherwise noted
2
Rating
DD35
no valid oscillation is detected, the MCU will start using the internal self
Table A-21. Startup Characteristics
MC9S12XDP512 Data Sheet, Rev. 2.21
= 5 V, T= 25 C
PORA
are derived from the V
uposc
.
RSTL
PW
Symbol
PW
n
t
WRS
t
RST
fws
RSTL
IRQ
the CRG module generates an internal
Min
192
25
—
—
2
1
DD
Appendix A Electrical Characteristics
supply. They are also valid
Typ
50
—
—
—
—
Max
196
14
—
—
—
Unit
n
t
t
ns
osc
cyc
osc
1267
s