MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 958

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.69 Port AD1 Data Direction Register 1 (DDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures pins PAD as either input or output.
23.0.5.70 Port AD1 Reduced Drive Register 0 (RDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the
port is used as input this bit is ignored.
960
RDR0AD1[23:16]
DDR1AD1[15:8]
Reset
Reset
Field
Field
W
W
R
7–0
R
7–0
DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19
RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116
0
0
7
7
Data Direction Port AD1 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has
Reduced Drive Port AD1 Register 0
0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
read on PTAD11 register, when changing the DDR1AD1 register.
to be set to logic level “1”.
Figure 23-72. Port AD1 Reduced Drive Register 0 (RDR0AD1)
Figure 23-71. Port AD1 Data Direction Register 1 (DDR1AD1)
0
0
6
6
Table 23-62. DDR1AD1 Field Descriptions
Table 23-63. RDR0AD1 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
5
0
0
4
4
Description
Description
0
0
3
3
0
0
2
2
Freescale Semiconductor
0
0
1
1
DDR1AD18
0
0
0
0