MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 443

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

10.3.2.18 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Freescale Semiconductor
Module Base + 0x0014 (CANIDMR0)
AC[7:0]
Field
7:0
Reset
Reset
Reset
Reset
Figure 10-22. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
W
W
W
W
R
R
R
R
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
AM7
AM7
AM7
AM7
0
0
0
0
7
7
7
7
Table 10-21. CANIDAR4–CANIDAR7 Register Field Descriptions
AM6
AM6
AM6
AM6
0
0
0
0
6
6
6
6
MC9S12XDP512 Data Sheet, Rev. 2.21
AM5
AM5
AM5
AM5
0
0
0
0
5
5
5
5
Chapter 10 Freescale’s Scalable Controller Area Network (S12MSCANV3)
AM4
AM4
AM4
AM4
Description
4
0
4
0
4
0
4
0
AM3
AM3
AM3
AM3
0
0
0
0
3
3
3
3
AM2
AM2
AM2
AM2
0
0
0
0
2
2
2
2
AM1
AM1
AM1
AM1
0
0
0
0
1
1
1
1
AM0
AM0
AM0
AM0
0
0
0
0
0
0
0
0
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