MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 1142

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
27.4.3
The ACCERR flag will be set during the command write sequence if any of the following illegal steps are
performed, causing the command write sequence to immediately abort:
The ACCERR flag will not be set if any Flash register is read during a valid command write sequence.
The ACCERR flag will also be set if any of the following events occur:
If the Flash memory is read during execution of an algorithm (CCIF = 0), the read operation will return
invalid data and the ACCERR flag will not be set.
If the ACCERR flag is set in the FSTAT register, the user must clear the ACCERR flag before starting
another command write sequence (see
The PVIOL flag will be set after the command is written to the FCMD register during a command write
sequence if any of the following illegal operations are attempted, causing the command write sequence to
immediately abort:
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1. Writing to a Flash address before initializing the FCLKDIV register.
2. Writing a byte or misaligned word to a valid Flash address.
3. Starting a command write sequence while a data compress operation is active.
4. Starting a command write sequence while a sector erase abort operation is active.
5. Writing a Flash address in step 1 of a command write sequence that is not the same relative address
6. Writing to any Flash register other than FCMD after writing to a Flash address.
7. Writing a second command to the FCMD register in the same command write sequence.
8. Writing an invalid command to the FCMD register.
9. When security is enabled, writing a command other than mass erase to the FCMD register when
10. Writing to a Flash address after writing to the FCMD register.
11. Writing to any Flash register other than FSTAT (to clear CBEIF) after writing to the FCMD
12. Writing a 0 to the CBEIF flag in the FSTAT register to abort a command write sequence.
1. Launching the sector erase abort command while a sector erase operation is active which results in
2. The MCU enters stop mode and a program or erase operation is in progress. The operation is
1. Writing the program command if an address written in the command write sequence was in a
2. Writing the sector erase command if an address written in the command write sequence was in a
3. Writing the mass erase command to a Flash block while any Flash protection is enabled in the
as the first one written in the same command write sequence.
the write originates from a non-secure memory location or from the Background Debug Mode.
register.
the early termination of the sector erase operation (see
Command”).
aborted immediately and any pending command is purged (see
protected area of the Flash memory
protected area of the Flash memory
block
Illegal Flash Operations
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 27.3.2.6, “Flash Status Register
Section 27.4.2.6, “Sector Erase Abort
Section 27.5.2, “Stop
(FSTAT)”).
Freescale Semiconductor
Mode”).