MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 1018

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.50 Port J Data Register (PTJ)
Read: Anytime.
Write: Anytime.
Port J pins 7–6 are associated with the CAN4, IIC0, the routed CAN0 modules. These pins can be used as
general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read except for bits 5-2 which read “0”.
1020
Routed
PIFH[7:0]
CAN4
CAN0
PJ[7:6]
Reset
Field
Field
7–0
7–6
IIC0
W
R
TXCAN4
TXCAN0
SCL0
PTJ7
Interrupt Flags Port H
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC0, the routed CAN0 and the general
purpose I/O function if the CAN4 module is enabled.
The IIC0 function (SCL0 and SDA0) takes precedence over the routed CAN0 and the general purpose I/O
function if the IIC0 is enabled. If the IIC0 module takes precedence the SDA0 and SCL0 outputs are configured
as open drain outputs. Refer to IIC section for details.
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if
the routed CAN0 module is enabled. Refer to MSCAN section for details.
0
7
Writing a logic level “1” clears the associated flag.
= Unimplemented or Reserved
RXCAN4
RXCAN0
SDA0
PTJ6
0
6
Figure 24-52. Port J Data Register (PTJ)
Table 24-46. PIFH Field Descriptions
Table 24-47. PTJ Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
0
5
0
0
4
Description
Description
0
0
3
0
0
2
Freescale Semiconductor
PTJ1
0
1
PTJ0
0
0