MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 206

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 XGATE (S12XGATEV2)
6.5
6.5.1
XGATE threads are triggered by interrupt requests which are routed to the XGATE module (see
S12X_INT Section). Only a subset of the MCU’s interrupt requests can be routed to the XGATE. Which
specific interrupt requests these are and which channel ID they are assigned to is documented in Section
“Interrupts” of the SoC Guide.
6.5.2
There are three types of interrupt requests which can be triggered by the XGATE module:
All XGATE interrupts can be disabled by the XGIE bit in the XGATE module control register (XGMCTL,
see
6.6
The XGATE debug mode is a feature to allow debugging of application code.
6.6.1
In debug mode the RISC core will be halted and the following debug features will be enabled:
1. Only possible if MCU is unsecured
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4. Channel interrupts
5. Software triggers
6. Software error interrupt
Section 6.3.1.1, “XGATE Control Register
•
For each XGATE channel there is an associated interrupt flag in the XGATE interrupt flag vector
(XGIF, see
set through the "SIF" instruction by the RISC core. They are typically used to flag an interrupt to
the S12X_CPU when the XGATE has completed one of its tasks.
Software triggers are interrupt flags, which can be set and cleared by software (see
“XGATE Software Trigger Register
by the S12X_CPU software. However these interrupts can also be routed to the S12X_CPU (see
S12X_INT Section) and triggered by the XGATE software.
The software error interrupt signals to the S12X_CPU the detection of an error condition in the
XGATE application code (see
Read and Write accesses to RISC core registers (XGCCR, XGPC, XGR1–XGR7)
All RISC core registers can be modified. Leaving debug mode will cause the RISC core to continue
program execution with the modified register values.
Interrupts
Debug Mode
Incoming Interrupt Requests
Outgoing Interrupt Requests
Debug Features
Section 6.3.1.4, “XGATE Channel Interrupt Flag Vector
MC9S12XDP512 Data Sheet, Rev. 2.21
Section 6.4.5, “Software Error
(XGSWT)”). They are typically used to trigger XGATE tasks
(XGMCTL)”).
Detection”).
(XGIF)”). These flags can be
Freescale Semiconductor
Section 6.3.1.5,
1