MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 85

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

2.3.2.1
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR + 1). PLLCLK will not be below the minimum VCO frequency (f
Read: Anytime
Write: Anytime except if PLLSEL = 1
2.3.2.2
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: Anytime
Write: Anytime except when PLLSEL = 1
Freescale Semiconductor
Reset
Reset
W
W
R
R
PLLCLK
CRG Synthesizer Register (SYNR)
CRG Reference Divider Register (REFDV)
0
0
0
0
7
7
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Write to this register initializes the lock detector bit and the track detector
bit.
Write to this register initializes the lock detector bit and the track detector
bit.
=
2xOSCCLKx
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 2-5. CRG Reference Divider Register (REFDV)
Figure 2-4. CRG Synthesizer Register (SYNR)
----------------------------------- -
REFDV
SYNR
REFDV5
MC9S12XDP512 Data Sheet, Rev. 2.21
SYN5
0
0
5
5
+
+
1
1
REFDV4
SYN4
NOTE
NOTE
NOTE
0
0
4
4
REFDV3
SYN3
0
0
3
3
Chapter 2 Clocks and Reset Generator (S12CRGV6)
REFDV2
SYN2
0
0
2
2
SCM
REFDV1
SYN1
).
0
0
1
1
REFDV0
SYN0
0
0
0
0
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