MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 767

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
20.4.2
The S12XDBG contains four comparators, A, B, C, and D. Each comparator can be configured to monitor
either S12XCPU or XGATE buses using the SRC bit in the corresponding comparator control register.
Each comparator compares the selected address bus with the address stored in DBGXAH, DBGXAM, and
DBGXAL. Furthermore, comparators A and C also compare the data buses to the data stored in DBGXDH,
DBGXDL and allow masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses.
The comparator match control logic (see
an exact address or an address range, whereby either an access inside or outside the specified range
generates a match condition. The comparator configuration is controlled by the control register contents
and the range control by the DBGC2 contents.
On a match a trigger can initiate a transition to another state sequencer state (see
comparator control register also allows the type of access to be included in the comparison through the use
of the RWE, RW, SZE, and SZ bits. The RWE bit controls whether read or write comparison is enabled
for the associated comparator and the RW bit selects either a read or write access for a valid match.
Similarly the SZE and SZ bits allows the size of access (word or byte) to be considered in the compare.
Only comparators B and D feature SZE and SZ.
The TAG bit in each comparator control register is used to determine the triggering condition. By setting
TAG, the comparator will qualify a match with the output of opcode tracking logic and a trigger occurs
Freescale Semiconductor
TAGHITS
EXTERNAL TAGHI / TAGLO
XGATE S/W BREAKPOINT REQUEST
SECURE
S12XCPU BUS
XGATE BUS
READ TRACE DATA (DBG READ DATA BUS)
Comparator Modes
COMPARATOR A
COMPARATOR B
COMPARATOR C
COMPARATOR D
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 20-22. S12XDBG Overview
Figure
20-22) configures comparators to monitor the buses for
MATCH0
MATCH1
MATCH2
MATCH3
CONTROL
TRIGGER
LOGIC
TAG &
Chapter 20 S12X Debug (S12XDBGV3) Module
TRIGGER
STATE
BREAKPOINT REQUESTS
S12XCPU & XGATE
Section
STATE SEQUENCER
TRACE BUFFER
TAGS
STATE
20.4.3”). The
TRACE
CONTROL
TRIGGER
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