HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 968

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
Section 21 High-performance User Debug Interface (H-UDI)
The maximum frequency of TCK (TMS, TDI, TDO) is 20 MHz. Make the TCK or CPG setting of
this LSI such that the TCK frequency is lower than that of this LSI’s on-chip peripheral module
clock.
21.1.4
Table 21.2 shows the H-UDI registers. Except for SDBPR, these registers are mapped in the
control register space and can be referenced by the CPU.
Table 21.2 H-UDI Registers
Name
Instruction
register
Data register
H
Data register
L
Bypass
register
Interrupt
source
register *
Boundary
scan register *
Notes: 1. Initialized when the TRST pin goes low or when the TAP is in the Test-Logic-Reset
Rev.7.00 Oct. 10, 2008 Page 882 of 1074
REJ09B0366-0700
4
2. The value read from H-UDI is fixed (H'FFFFFFFD).
3. Using the H-UDI interrupt command, a 1 can be written to the least significant bit.
4. SH7750R only
Register Configuration
the rating of the pull-up resistor. Although this current has no effect on the chip's
operation, unnecessary current will be dissipated.
state.
4
Abbre-
viation
SDIR
SDDR/
SDDRH
SDDRL R/W H'FFF0000A H'1FF0000A 16
SDBPR —
SDINT
SDBSR —
R/W
R
R/W H'FFF00008 H'1FF00008 32/16
R/W H'FFF00014 H'1FF00014 16
P4
Address
H'FFF00000 H'1FF00000 16
CPU Side
Area 7
Address
Access
Size
Initial
Value *
H'FFFF
Unde-
fined
Unde-
fined
Unde-
fined
H'0000
Unde-
fined
1
R/W
R/W
R/W
W *
R/W
3
Access
Size
32
1
32
H-UDI Side
Initial
Value *
H'FFFFFFFD
(Fixed
value *
H'00000000
Undefined
2
1
)

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