HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 653

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14.3
When a DMA transfer request is issued, the DMAC starts the transfer according to the
predetermined channel priority order. It ends the transfer when the transfer end conditions are
satisfied. Transfers can be requested in three modes: auto-request, external request, and on-chip
peripheral module request. There are two modes for DMA transfer: single address mode and dual
address mode. Either burst mode or cycle steal mode can be selected as the bus mode.
14.3.1
After the desired transfer conditions have been set in the DMA source address register (SAR),
DMA destination address register (DAR), DMA transfer count register (DMATCR), DMA
channel control register (CHCR), and DMA operation register (DMAOR), the DMAC transfers
data according to the following procedure:
1. The DMAC checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, NMIF = 0, AE =
2. When a transfer request is issued and transfer has been enabled, the DMAC transfers one
3. When the specified number of transfers have been completed (when the DMATCR value
4. If a DMAC address error or NMI interrupt occurs, the transfer is suspended. Transfer is also
Figure 14.2 shows a flowchart of this procedure.
Note: If transfer request is issued while transfer is disabled, the transfer enable wait state
0).
transfer unit of data (determined by the setting of TS2–TS0). In auto-request mode, the transfer
begins automatically when the DE bit and DME bit are set to 1. The DMATCR value is
decremented by 1 for each transfer. The actual transfer flow depends on the address mode and
bus mode.
reaches 0), the transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DMTE
interrupt request is sent to the CPU.
suspended when the DE bit in CHCR or the DME bit in DMAOR is cleared to 0. In the event
of an address error, a DMAE interrupt request is forcibly sent to the CPU.
(transfer suspended state) is entered. Transfer is started when subsequently enabled (by
setting DE = 1, DME = 1, TE = 0, NMIF = 0, AE = 0)
Operation
DMA Transfer Procedure
Section 14 Direct Memory Access Controller (DMAC)
Rev.7.00 Oct. 10, 2008 Page 567 of 1074
REJ09B0366-0700