HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 328

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Section 8 Pipelining
Table 8.2
Legend:
O: Can be executed in parallel
X: Cannot be executed in parallel
8.3
There are three basic clocks in this processor: the I-clock, B-clock, and P-clock. Each hardware
unit operates on one of these clocks, as follows:
• I-clock: CPU, FPU, MMU, caches
• B-clock: External bus controller
• P-clock: Peripheral units
The frequency ratios of the three clocks are determined with the frequency control register
(FRQCR). In this section, machine cycles are based on the I-clock unless otherwise specified. For
details of FRQCR, see section 10, Clock Oscillation Circuits.
Instruction execution cycles are summarized in table 8.3. Penalty cycles due to a pipeline stall or
freeze are not considered in this table.
• Issue rate: Interval between the issue of an instruction and that of the next instruction
• Latency: Interval between the issue of an instruction and the generation of its result
• Instruction execution pattern (see figure 8.2)
• Locked pipeline stages (see table 8.3)
• Interval between the issue of an instruction and the start of locking (see table 8.3)
• Lock time: Period of locking in machine cycle units (see table 8.3)
Rev.7.00 Oct. 10, 2008 Page 242 of 1074
REJ09B0366-0700
1st
Instruction
(completion)
Execution Cycles and Pipeline Stalling
Parallel-Executability
MT
EX
BR
LS
FE
CO
MT
O
O
O
O
O
X
EX
O
O
O
O
X
X
2nd Instruction
BR
O
O
O
O
X
X
LS
O
O
O
O
X
X
FE
O
O
O
O
X
X
CO
X
X
X
X
X
X