HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 817

MPU 1.5/3.3V 0K I-TEMP PB-FREE 2

HD6417750RF200DV

Manufacturer Part Number
HD6417750RF200DV
Description
MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
Manufacturer
Renesas Electronics America
Series
SuperH® SH7750r
Datasheet

Specifications of HD6417750RF200DV

Core Processor
SH-4
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, FIFO, SCI, SmartCard
Peripherals
DMA, POR, WDT
Number Of I /o
28
Program Memory Type
ROMless
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.35 V ~ 1.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
208-QFP Exposed Pad, 208-eQFP, 208-HQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD6417750RF200DV
Manufacturer:
FREESCALE
Quantity:
450
16.2.4
SCFTDR2 is an 8-bit 16-stage FIFO register that stores data for serial transmission.
If SCTSR2 is empty when transmit data has been written to SCFTDR2, the SCIF transfers the
transmit data written in SCFTDR2 to SCTSR2 and starts serial transmission.
SCFTDR2 is a write-only register, and cannot be read by the CPU.
The next data cannot be written when SCFTDR2 is filled with 16 bytes of transmit data. Data
written in this case is ignored.
The contents of SCFTDR2 are undefined after a power-on reset or manual reset.
16.2.5
SCSMR2 is a 16-bit register used to set the SCIF's serial transfer format and select the baud rate
generator clock source.
SCSMR2 can be read or written to by the CPU at all times.
SCSMR2 is initialized to H'0000 by a power-on reset or manual reset. It is not initialized in
standby mode or in the module standby state.
Bits 15 to 7—Reserved: These bits are always read as 0, and should only be written with 0.
Initial value:
Initial value:
Transmit FIFO Data Register (SCFTDR2)
Serial Mode Register (SCSMR2)
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
15
W
R
R
7
0
7
0
CHR
R/W
14
W
R
6
0
6
0
Section 16 Serial Communication Interface with FIFO (SCIF)
R/W
PE
13
W
R
5
0
5
0
R/W
O/E
12
W
R
4
0
4
0
Rev.7.00 Oct. 10, 2008 Page 731 of 1074
STOP
R/W
11
W
R
3
0
3
0
10
W
R
R
2
0
2
0
REJ09B0366-0700
CKS1
R/W
W
R
1
9
0
1
0
CKS0
R/W
W
R
0
8
0
0
0

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