HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 507

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Reading RTCSR, RTCNT, RTCOR, and RFCR: A 16-bit access must always be used when
reading RTCSR, RTCNT, RTCOR, or RFCR. Undefined bits are read as 0.
13.3
13.3.1
This LSI supports both big-endian mode, in which the most significant byte (MSByte) is at the 0
address end in a string of byte data, and little-endian mode, in which the least significant byte
(LSByte) is at the 0 address end. The mode is set by means of the MD5 external pin in a power-on
reset by the RESET pin, big-endian mode being set if the MD5 pin is low, and little-endian mode
if it is high.
A data bus width of 8, 16, 32, or 64 bits can be selected for normal memory, 16, 32, or 64 bits for
DRAM, 32 or 64 bits for synchronous DRAM, and 8 or 16 bits for the PCMCIA interface. Data
alignment is carried out according to the data bus width and endian mode of each device. If the
data bus width is smaller than the access size, a number of bus cycles will be generated
automatically until the access size is reached. In this case, address incrementing is performed
automatically according to the bus width as access is performed. For example, if longword access
is performed in an 8-bit bus width area using the SRAM interface, four accesses are executed, with
the address automatically incremented by 1 each time. In 32-byte transfer, a total of 32 bytes of
data are transferred consecutively according to the set bus width. The first access is performed on
the data for which there was an access request, and the remaining accesses are performed on 32-
byte boundary data using wraparound. Bus release or refresh operations are not performed
between these transfers. Data alignment and data length conversion between the different
interfaces is performed automatically. Quadword access is used only in transfer by the DMAC.
The relationship between the endian mode, device data length, and access unit, is shown in tables
13.7 to 13.14.
RTCSR,
RTCNT,
RTCOR
RFCR
Operation
Endian/Access Size and Data Alignment
15
15
1
1
Figure 13.5 Writing to RTCSR, RTCNT, RTCOR, and RFCR
14
14
0
0
13
13
1
1
12
12
0
0
11
11
0
0
10
10
1
1
9
0
9
8
1
8
7
7
Rev.7.00 Oct. 10, 2008 Page 421 of 1074
Section 13 Bus State Controller (BSC)
6
6
Write data
5
5
Write data
4
4
3
3
REJ09B0366-0700
2
2
1
1
0
0