HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 947

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 31 to 0—Break Data Mask B31 to B0 (BDMB31–BDMB0): These bits specify whether the
corresponding bit of the channel B break data B31 to B0 (BDB31–BDB0) set in BDRB is to be
masked.
Bit 31–0: BDMBn
0
1
Note: When the data bus value is included in the break conditions, the operand size should be
20.2.11 Break Bus Cycle Register B (BBRB)
BBRB is the channel B bus break register. The bit configuration is the same as for BBRA.
20.2.12 Break Control Register (BRCR)
Legend:
The break control register (BRCR) is a 16-bit readable/writable register that specifies (1) whether
channels A and B are to be used as two independent channels or in a sequential condition, (2)
whether the break is to be effected before or after instruction execution, (3) whether the BDRB
register is to be included in the channel B break conditions, and (4) whether the user break debug
function is to be used. BRCR also contains condition match flags. The CMFA, CMFB, and UBDE
bits in BRCR are initialized to 0 by a power-on reset, but retain their value in standby mode. The
Initial value:
Initial value:
specified. When byte size is specified, set the same data in bits 15–8 and 7–0 of BDRB and
BDMRB.
*: Undefined
R/W:
R/W:
Bit:
Bit:
CMFA
DBEB
Description
Channel B break data bit BDBn is included in break conditions
Channel B break data bit BDBn is masked, and not included in break
conditions
R/W
R/W
15
0
7
*
CMFB
PCBB
R/W
R/W
14
0
6
*
13
—
—
R
R
0
5
0
12
—
—
R
R
0
4
0
Rev.7.00 Oct. 10, 2008 Page 861 of 1074
Section 20 User Break Controller (UBC)
SEQ
R/W
11
—
R
0
3
*
PCBA
R/W
10
—
R
2
0
*
REJ09B0366-0700
—
—
R
R
9
0
1
0
n = 31 to 0
UBDE
R/W
—
R
8
0
0
0