HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 479

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

Bits 25 to 23—Area 5 Wait Control (A5W2–A5W0): These bits specify the number of wait
states to be inserted for area 5. For details on MPX interface setting, see table 13.6, MPX Interface
is Selected (Areas 0 to 6).
Bit 25: A5W2
0
1
Bits 22 to 20—Area 5 Burst Pitch (A5B2–A5B0): These bits specify the number of wait states to
be inserted from the second data access onward in a burst transfer with the burst ROM interface
selected.
Bit 22: A5B2
0
1
Bit 24: A5W1
0
1
0
1
Bit 21: A5B1
0
1
0
1
Bit 23: A5W0
0
1
0
1
0
1
0
1
Bit 20: A5B0
0
1
0
1
0
1
0
1
Inserted Wait States
0
1
2
3
6
9
12
15 (Initial value)
Wait States Inserted from Second
Data Access Onward
0
1
2
3
4
5
6
7 (Initial value)
Rev.7.00 Oct. 10, 2008 Page 393 of 1074
Burst Cycle (Excluding First Cycle)
Section 13 Bus State Controller (BSC)
Description
First Cycle
Description
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
REJ09B0366-0700
RDY Pin
Ignored
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled