HD6417750RF200DV Renesas Electronics America, HD6417750RF200DV Datasheet - Page 54

• Manufacturer Part Number: HD6417750RF200DV
• Description: MPU 1.5/3.3V 0K I-TEMP PB-FREE 2
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7750r

Specifications of HD6417750RF200DV

• Core Processor: SH-4
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, FIFO, SCI, SmartCard
• Peripherals: DMA, POR, WDT
• Number Of I /o: 28
• Program Memory Type: ROMless
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.35 V ~ 1.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-QFP Exposed Pad, 208-eQFP, 208-HQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

9.9
Section 10 Clock Oscillation Circuits
10.1 Overview........................................................................................................................... 287
10.2 Overview of CPG.............................................................................................................. 289
10.3 Clock Operating Modes .................................................................................................... 293
10.4 CPG Register Description................................................................................................. 295
10.5 Changing the Frequency ................................................................................................... 298
10.6 Output Clock Control........................................................................................................ 299
10.7 Overview of Watchdog Timer .......................................................................................... 300
10.8 WDT Register Descriptions .............................................................................................. 301
10.9 Using the WDT ................................................................................................................. 305
10.10 Notes on Board Design ..................................................................................................... 307
10.11 Usage Notes ...................................................................................................................... 309
Section 11 Realtime Clock (RTC)
11.1 Overview........................................................................................................................... 311
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REJ09B0366-0700
9.8.5
Usage Notes ...................................................................................................................... 286
9.9.1
10.1.1 Features................................................................................................................ 287
10.2.1 Block Diagram of CPG........................................................................................ 289
10.2.2 CPG Pin Configuration ........................................................................................ 292
10.2.3 CPG Register Configuration ................................................................................ 292
10.4.1 Frequency Control Register (FRQCR)................................................................. 295
10.5.1 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is Off) ........... 298
10.5.2 Changing PLL Circuit 1 Starting/Stopping (When PLL Circuit 2 Is On)............ 298
10.5.3 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is On) ...................... 299
10.5.4 Changing Bus Clock Division Ratio (When PLL Circuit 2 Is Off) ..................... 299
10.5.5 Changing CPU or Peripheral Module Clock Division Ratio ............................... 299
10.7.1 Block Diagram..................................................................................................... 300
10.7.2 Register Configuration......................................................................................... 301
10.8.1 Watchdog Timer Counter (WTCNT)................................................................... 301
10.8.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 302
10.8.3 Notes on Register Access..................................................................................... 305
10.9.1 Standby Clearing Procedure ................................................................................ 305
10.9.2 Frequency Changing Procedure ........................................................................... 306
10.9.3 Using Watchdog Timer Mode.............................................................................. 306
10.9.4 Using Interval Timer Mode ................................................................................. 307
10.11.1 Invalid Manual Reset Triggered by Watchdog Timer (SH7750 and SH7750S).. 309
11.1.1 Features................................................................................................................ 311
Hardware Standby Mode Timing (SH7750S, SH7750R Only) ........................... 283
Note on Current Consumption ............................................................................. 286
.................................................................................. 311
........................................................................... 287