ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet - Page 41

• Manufacturer Part Number: ATTINY2313A-PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ATtiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.2.4
8.3
8.3.1
8.4
8246A–AVR–11/09
Internal Voltage Reference
Watchdog Timer
Watchdog Reset
Voltage Reference Enable Signals and Start-up Time
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period t
“Interrupts” on page 47
Figure 8-6.
ATtiny2313A/4313 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator. The bandgap voltage varies
with supply voltage and temperature.
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in
reference is not always turned on. The reference is on during the following situations:
Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the
reference to start up before the output from the Analog Comparator. To reduce power consump-
tion in Power-down mode, the user can avoid the three conditions above to ensure that the
reference is turned off before entering Power-down mode.
The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in
8-3 on page
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny2313A/4313 resets and executes from the Reset
Vector. For timing details on the Watchdog Reset, refer to
1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).
2. When the internal reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
CC
46. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Reset During Operation
for details on operation of the Watchdog Timer.
“System and Reset Characteristics” on page
CK
Table 8-3 on page
198. To save power, the
46.
TOUT
Table
. See
41