ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet - Page 175

• Manufacturer Part Number: ATTINY2313A-PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ATtiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.6.3
8246A–AVR–11/09
Reading Device Signature Imprint Table from Firmware
To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and
repeat the procedure above. If successful, the contents of the destination register are as follows.
Refer to
To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and
repeat the previous procedure. If successful, the contents of the destination register are as
follows.
Refer to
Byte.
To read the contents of the device signature imprint table, follow the below procedure:
The RSIG and SPMEN bits will auto-clear after three CPU cycles. When RSIG and SPMEN are
cleared, LPM will work as described in the “AVR Instruction Set” description.
See program example below.
Note:
Bit
Rd
Bit
Rd
Assembly Code Example
1. Load the Z-pointer with the table index.
2. Set RSIG and SPMEN bits in SPMCSR.
3. Issue an LPM instruction within three clock cycles.
4. Wait three clock cycles for SPMEN bits to be cleared.
5. Read table data from the LPM destination register.
DSIT_read:
; Uses Z-pointer as table index
ldi
ldi
; Preload SPMCSR bits into R16, then write to SPMCSR
ldi
out SPMCSR, r16
; Issue LPM. Table data will be returned into r17
lpm r17, Z
ret
See
Table 20-4 on page 179
Table 20-3 on page 179
“Code Examples” on page
ZH, 0
ZL, 1
r16, (1<<RSIG)|(1<<SPMEN)
FHB7
FEB7
7
7
FHB6
FEB6
6
6
for detailed description and mapping of the Fuse High Byte.
FHB5
FEB5
for detailed description and mapping of the Fuse Extended
5
5
6.
FHB4
FEB4
4
4
FHB3
FEB3
3
3
FHB2
FEB2
2
2
FHB1
FEB1
1
1
FHB0
FEB0
0
0
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