ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet - Page 146

• Manufacturer Part Number: ATTINY2313A-PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ATtiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.4
146
SPI Data Modes and Timing
ATtiny2313A/4313
Table 15-1.
Note:
There are four combinations of XCK (SCK) phase and polarity with respect to serial data, which
are determined by control bits UCPHA and UCPOL. The data transfer timing diagrams are
shown in
nal, ensuring sufficient time for data signals to stabilize. The UCPOL and UCPHA functionality is
summarized in
ongoing communication for both the Receiver and Transmitter.
Table 15-2.
Figure 15-1. UCPHA and UCPOL data transfer timing diagrams.
Operating Mode
Synchronous Master
mode
UCPOL
BAUD
f
UBRR
OSC
0
0
1
1
1. The baud rate is defined to be the transfer rate in bit per second (bps)
Figure
Data setup (TXD)
XCK
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
Equations for Calculating Baud Rate Register Setting
UCPOL and UCPHA Functionality-
Table
15-1. Data bits are shifted out and latched in on opposite edges of the XCK sig-
UCPHA
Baud rate (in bits per second, bps)
System Oscillator clock frequency
Contents of the UBRRH and UBRRL Registers, (0-4095)
15-2. Note that changing the setting of any of these bits will corrupt all
0
1
0
1
Equation for Calculating Baud
UCPOL=0
BAUD
SPI Mode
=
0
1
2
3
Rate
---------------------------------- -
2 UBRR
(
(1)
f
OSC
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Leading Edge
+
1
)
XCK
Data setup (TXD)
Data sample (RXD)
XCK
Data setup (TXD)
Data sample (RXD)
Equation for Calculating UBRRn
UBRR
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
UCPOL=1
=
Value
------------------- - 1
2BAUD
f
OSC
8246A–AVR–11/09
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