ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet - Page 149

• Manufacturer Part Number: ATTINY2313A-PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ATtiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.6
8246A–AVR–11/09
Data Transfer
Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXEN bit in the
UCSRB register is set to one. When the Transmitter is enabled, the normal port operation of the
TxD pin is overridden and given the function as the Transmitter's serial output. Enabling the
receiver is optional and is done by setting the RXEN bit in the UCSRB register to one. When the
receiver is enabled, the normal pin operation of the RxD pin is overridden and given the function
as the Receiver's serial input. The XCK will in both cases be used as the transfer clock.
After initialization the USART is ready for doing data transfers. A data transfer is initiated by writ-
ing to the UDR I/O location. This is the case for both sending and receiving data since the
transmitter controls the transfer clock. The data written to UDR is moved from the transmit buffer
to the shift register when the shift register is ready to send a new frame.
Note:
The following code examples show a simple USART in MSPIM mode transfer function based on
polling of the Data Register Empty (UDRE) Flag and the Receive Complete (RXC) Flag. The
USART has to be initialized before the function can be used. For the assembly code, the data to
be sent is assumed to be stored in Register R16 and the data received will be available in the
same register (R16) after the function returns.
The function simply waits for the transmit buffer to be empty by checking the UDRE Flag, before
loading it with new data to be transmitted. The function then waits for data to be present in the
receive buffer by checking the RXC Flag, before reading the buffer and returning the value.
To keep the input buffer in sync with the number of data bytes transmitted, the UDR register must
be read once for each byte transmitted. The input buffer operation is identical to normal USART
mode, i.e. if an overflow occurs the character last received will be lost, not the first data in the buf-
fer. This means that if four bytes are transferred, byte 1 first, then byte 2, 3, and 4, and the UDR is
not read before all transfers are completed, then byte 3 to be received will be lost, and not byte 1.
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