ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet

IC MCU AVR 2K FLASH 20MHZ 20DIP

ATTINY2313A-PU

Manufacturer Part Number
ATTINY2313A-PU
Description
IC MCU AVR 2K FLASH 20MHZ 20DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheets

Specifications of ATTINY2313A-PU

Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
18
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Controller Family/series
ATtiny
No. Of I/o's
18
Eeprom Memory Size
128Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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Features
High Performance, Low Power AVR
Advanced RISC Architecture
Data and Non-volatile Program and Data Memories
Peripheral Features
Special Microcontroller Features
I/O and Packages
Operating Voltage
Speed Grades
Industrial Temperature Range: -40°C to +85°C
Low Power Consumption
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– 2/4K Bytes of In-System Self Programmable Flash
– 128/256 Bytes In-System Programmable EEPROM
– 128/256 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes
– Four PWM Channels
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
– USI – Universal Serial Interface
– Full Duplex USART
– debugWIRE On-chip Debugging
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low-power Idle, Power-down, and Standby Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
– 18 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC, 20-pad MLF/VQFN
– 1.8 – 5.5V
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 10 MHz @ 2.7 – 5.5V
– 0 – 20 MHz @ 4.5 – 5.5V
– Active Mode
– Idle Mode
– Power-down Mode
• Endurance 10,000 Write/Erase Cycles
• Endurance: 100,000 Write/Erase Cycles
• 190 µA at 1.8V and 1MHz
• 24 µA at 1.8V and 1MHz
• 0.1 µA at 1.8V and +25°C
®
8-Bit Microcontroller
8-bit
Microcontroller
with 2/4K Bytes
In-System
Programmable
Flash
ATtiny2313A
ATtiny4313
Preliminary
Rev. 8246A–AVR–11/09

Related parts for ATTINY2313A-PU

ATTINY2313A-PU Summary of contents

Page 1

... Idle Mode • 24 µA at 1.8V and 1MHz – Power-down Mode • 0.1 µA at 1.8V and +25°C ® 8-Bit Microcontroller 8-bit Microcontroller with 2/4K Bytes In-System Programmable Flash ATtiny2313A ATtiny4313 Preliminary Rev. 8246A–AVR–11/09 ...

Page 2

... Port A output buffers have symmetrical drive characteristics with both high sink and source capability, except PA2 which has the RESET capability. To use pin PA2 as I/O pin, instead of RESET pin, program (“0”) RSTDISBL fuse. As inputs, Port A pins that are externally pulled low ATtiny2313A/4313 2 Pinout ATtiny2313A/4313 PDIP/SOIC (PCINT10/RESET/dW) PA2 1 2 ...

Page 3

... As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port D also serves the functions of various special features of the ATtiny2313A/4313 as listed on page 66. ...

Page 4

... Overview The ATtiny2313A/4313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313A/4313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...

Page 5

... RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313A/4313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATtiny2313A/4313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu- lators, and Evaluation kits. ...

Page 6

... PPM over 20 years at 85°C or 100 years at 25°C. 3.4 Disclaimer Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device has been characterized. ATtiny2313A/4313 6 8246A–AVR–11/09 ...

Page 7

CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle ...

Page 8

... Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. ATtiny2313A/4313 8 8246A–AVR–11/09 ...

Page 9

The AVR Status Register – SREG – is defined as: Bit 0x3F (0x5F) Read/Write Initial Value • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual ...

Page 10

... The three indirect address registers X, Y, and Z are defined as described in Figure 4-3. X-register Y-register Z-register ATtiny2313A/4313 10 shows the structure of the 32 general purpose working registers in the CPU. AVR CPU General Purpose Working Registers 7 R0 ...

Page 11

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local ...

Page 12

... Interrupt flags can also be cleared by writing a logic one to the flag bit position( cleared interrupt condition occurs while the corresponding interrupt enable bit is cleared, ATtiny2313A/4313 12 The Parallel Instruction Fetches and Instruction Executions ...

Page 13

Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) ...

Page 14

... A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set. ATtiny2313A/4313 14 8246A–AVR–11/09 ...

Page 15

... Since all AVR instructions are bits wide, the Flash is organized as 1/2K x 16. The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny2313A/4313 Program Counter (PC) is 10/11 bits wide, thus addressing the 1/2K program memory locations. data serial downloading using the SPI pins. ...

Page 16

... When using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 128/256 bytes of internal data SRAM in the ATtiny2313A/4313 are all accessible through all these addressing modes. The Register File is described in Figure 5-2. ...

Page 17

... Figure 5-3. 5.3 EEPROM Data Memory The ATtiny2313A/4313 contains 128/256 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...

Page 18

... EEPROM operations. The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre- quency is within the requirements described in page 30. ATtiny2313A/4313 18 Table 5-1 on page 22. The EEPE bit remains set until the erase Table 5-1 on page 22). The EEPE bit remains set until the erase operation “ ...

Page 19

Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts will ...

Page 20

... Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used reset occurs while a write operation is in progress, the write operation will be com- pleted provided that the power supply voltage is sufficient. ATtiny2313A/4313 20 (1) r16,EEDR (1) ...

Page 21

... Bit 7 – EEAR7: EEPROM Address This is the most significant EEPROM address bit of ATtiny4313. In devices with less EEPROM, i.e. ATtiny2313A, this bit is reserved and will always read zero. The initial value of the EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written before the EEPROM is accessed. • ...

Page 22

... Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved for future use and will always read ATtiny2313A/4313. For compatibil- ity with future AVR devices, always write this bit to zero. After reading, mask out this bit. • Bit 6 – Res: Reserved Bit This bit is reserved in the ATtiny2313A/4313 and will always read as zero. • ...

Page 23

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the ...

Page 24

... Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. ATtiny2313A/4313 24 presents the principal clock systems in the AVR and their distribution. All of the clocks 33. Clock Distribution ...

Page 25

Clock Sources The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules. Table 6-1. ...

Page 26

... Using calibration methods as described in application notes available at www.atmel.com/avr it is possi- ble to achieve ± 2% accuracy at any given V as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the ATtiny2313A/4313 26 External Clock Drive Configuration NC ...

Page 27

Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page Table 6-3. Note: When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 6-4. Table 6-4. ...

Page 28

... Table 6-6. CKSEL3..1 (1) 100 101 110 111 Note: The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 6-7. ATtiny2313A/4313 28 Table 6-6 on page Crystal Oscillator Connections C2 C1 Crystal Oscillator Operating Modes Frequency Range (MHz) 0.4 - 0.9 0.9 - 3.0 3 ...

Page 29

... Notes: 6.3 System Clock Prescaler The ATtiny2313A/4313 has a system clock prescaler, and the system clock can be divided by setting the decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...

Page 30

... Read/Write Initial Value • Bit 7 – Res: Reserved Bit This bit is reserved bit in ATtiny2313A/4313 and it will always read zero. • Bits 6:0 – CAL[6:0]: Oscillator Calibration Value Writing the calibration byte to this address will trim the internal Oscillator to remove process vari- ations from the Oscillator frequency ...

Page 31

... CLKPCE bit. • Bits 6:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits These bits define the division factor between the selected clock source and the internal system clock ...

Page 32

... Table 6-9. CLKPS3 ATtiny2313A/4313 32 Clock Prescaler Select (Continued) CLKPS2 CLKPS1 CLKPS0 Clock Division Factor 1 Reserved 0 Reserved 1 Reserved 8246A–AVR–11/09 ...

Page 33

... MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. 7.1 Sleep Modes Figure 6-1 on page 24 ATtiny2313A/4313. The figure is helpful in selecting an appropriate sleep mode. shows the different sleep modes and their wake up sources. Table 7-1. Sleep Mode Idle ...

Page 34

... Resources used by the peripheral will remain occupied. The peripheral should in most cases be disabled before stopping the clock. Clearing the PRR bit wakes up the peripheral and puts it in the same state as before shutdown. ATtiny2313A/4313 34 167. This will reduce power consumption in Idle level has dropped during the sleep period ...

Page 35

Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the over- all power consumption. See sleep modes, the clock is already stopped. 7.4 Minimizing Power Consumption There are several issues to consider when trying to ...

Page 36

... These bits are reserved and will always read zero. • Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. ATtiny2313A/4313 input pin can cause significant current even in active mode. Digital CC ...

Page 37

Bit 2 – PRTIM0: Power Reduction Timer/Counter0 Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown. • Bit 1 – PRUSI: Power Reduction USI ...

Page 38

... This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif- ferent selections for the delay period are presented in ATtiny2313A/4313 38 Figure 8-1 shows the reset logic. Electrical parameters of the Table 21-3 on page 198 ...

Page 39

... Reset Sources The ATtiny2313A/4313 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length when RESET function is enabled • ...

Page 40

... Figure 8-4. 8.2.3 Brown-out Detection ATtiny2313A/4313 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection ...

Page 41

... Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog Reset, the ATtiny2313A/4313 resets and executes from the Reset Vector. For timing details on the Watchdog Reset, refer to 8246A– ...

Page 42

... In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A timed sequence is needed when changing the Watchdog Time-out period. To change the Watchdog Time-out, the following procedure must be followed: ATtiny2313A/4313 42 WDT Configuration as a Function of the Fuse Settings of WDTON ...

Page 43

In the same operation, write a logical one to WDCE and WDE. Even though the b. Within the next four clock cycles, in the same operation, write the WDP bits as 8.4.2 Code Example The following code example shows ...

Page 44

... Initial Value • Bits 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • ...

Page 45

To avoid the Watchdog Reset, WDIE must be set after each interrupt. Table 8-2. WDE • Bit 4 – WDCE: Watchdog Change Enable This bit must be set when ...

Page 46

... Table 8-3. WDP3 Note: ATtiny2313A/4313 46 Watchdog Timer Prescale Select Number of WDT Oscillator WDP2 WDP1 WDP0 selected, one of the valid settings below 0b1010 will be used. Typical Time-out at Cycles cycles cycles cycles 64 ms 16K cycles 0.125 s 32K cycles 0.25 s 64K cycles 0.5 s 128K cycles 1 ...

Page 47

... Interrupts This section describes the specifics of the interrupt handling as performed in ATtiny2313A/4313. For a general explanation of the AVR interrupt handling, refer to on page 9.1 Interrupt Vectors The interrupt vectors of ATtiny2313A/4313 are described in Table 9-1. Vector No case the program never enables an interrupt source, the Interrupt Vectors will not be used and, consequently, regular program code can be placed at these locations. 8246A– ...

Page 48

... The most typical and general setup for the Interrupt Vector Addresses in ATtiny2313A/4313 shown below: Address Labels Code 0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 0x0006 0x0007 0x0008 0x0009 0x000A 0x000B 0x000C 0x000D 0x000E 0x000F 0x0010 0x0011 0x0012 0x0013 0x0014 ; 0x0013 0x0014 0x0015 0x0016 ...

Page 49

Low Level Interrupt A low level interrupt on INT0 or INT1 is detected asynchronously. This means that the interrupt source can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted ...

Page 50

... Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. Table 9-3. ISC01 9.3.2 GIMSK – General Interrupt Mask Register Bit 0x3B (0x5B) Read/Write Initial Value ATtiny2313A/4313 PUD SM1 SE SM0 ISC11 R/W R/W R/W R/W ...

Page 51

Bits 2..0 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit is set (one) and the I-bit in the Status ...

Page 52

... If PCINT17..11 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT17..11 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 9.3.5 PCMSK1 – Pin Change Mask Register 1 Bit 0x04 (0x24) Read/Write Initial Value ATtiny2313A/4313 – PCINT17 PCINT16 ...

Page 53

Bits 7:3 – Res: Reserved Bits These bits are reserved and will always read as zero. • Bits 2..0 – PCINT10..8: Pin Change Enable Mask 10..8 Each PCINT10..8 bit selects whether pin change interrupt is enabled on the corresponding ...

Page 54

... How each alternate function interferes with the port pin is described in Functions” on page nate functions. Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. ATtiny2313A/4313 54 and Ground as indicated in CC for a complete list of parameters. ...

Page 55

Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Note: 10.1.1 Configuring the Pin Each port pin consists ...

Page 56

... The maximum and minimum propagation delays are denoted t Figure 10-3. Synchronization when Reading an Externally Applied Pin value ATtiny2313A/4313 56 summarizes the control signals for the pin value. Port Pin Configurations ...

Page 57

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the ...

Page 58

... Insert nop for synchronization*/ _NOP(); /* Read port pins */ i = PINB; ... Note: ATtiny2313A/4313 58 or GND is not recommended, since this may cause excessive currents if the pin is CC r16,(1<<PB4)|(1<<PB1)|(1<<PB0) r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) PORTB,r16 ...

Page 59

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. In below is shown how the port pin control signals from the simplified be overridden by alternate functions. Figure 10-5. Alternate Port Functions ...

Page 60

... The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details. ATtiny2313A/4313 60 summarizes the function of the overriding signals. The pin and port indexes from are not shown in the succeeding tables. The overriding signals are generated internally ...

Page 61

Alternate Functions of Port A The Port A pins with alternate function are shown in Table 10-3. • Port A, Bit 0 – XTAL1/CLKI/PCINT8 • XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal ...

Page 62

... PTOE DIEOE DIEOV DI AIO Notes: 10.2.2 Alternate Functions of Port B The Port B pins with alternate function are shown in Table 10-5. ATtiny2313A/4313 62 relates the alternate functions of Port A to the overriding signals shown in 59. Overriding Signals for Alternate Functions in PA2..PA0 PA2/RESET/dW/PCINT10 PA1/XTAL2/PCINT9 (1) RSTDISBL + ...

Page 63

Table 10-5. • Port B, Bit 0 – AIN0/PCINT0 • AIN0: Analog Comparator Positive input. Configure the port pin as input with the internal pull- up switched off to avoid the digital port function from interfering with the function of ...

Page 64

... PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source for pin change interrupt 0. Table 10-6 shown in MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. ATtiny2313A/4313 64 and Table 10-7 relate the alternate functions of Port B to the overriding signals Figure 10-5 on page 59 ...

Page 65

Table 10-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 10-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8246A–AVR–11/09 Overriding Signals for Alternate Functions in PB7..PB4 PB7/USCK/ SCL/PCINT7 ...

Page 66

... INT1: External Interrupt Source 1. The PD3 pin can serve as an external interrupt source to the MCU. • PCINT14: Pin Change Interrupt Source 14. The PD3 pin can serve as an external interrupt source for pin change interrupt 2. ATtiny2313A/4313 66 Port D Pins Alternate Functions Port Pin ...

Page 67

Port D, Bit 4 – T0/PCINT15 • T0: Timer/Counter0 External Counter Clock input is enabled by setting (one) the bits CS02 and CS01 in the Timer/Counter0 Control Register (TCCR0). • PCINT15: Pin Change Interrupt Source 15. The PD4 pin ...

Page 68

... PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See figuring the Pin” on page 55 10.3.2 PORTA – Port A Data Register Bit 0x1B (0x3B) Read/Write Initial Value 10.3.3 DDRA – Port A Data Direction Register Bit 0x1A (0x3A) Read/Write Initial Value ATtiny2313A/4313 68 PD3/INT1/ PD2/INT0/XCK/CKOUT/ PCINT14 PCINT13 ...

Page 69

PINA – Port A Input Pins Address Bit 0x19 (0x39) Read/Write Initial Value 10.3.5 PORTB – Port B Data Register Bit 0x18 (0x38) Read/Write Initial Value 10.3.6 DDRB – Port B Data Direction Register Bit 0x17 (0x37) Read/Write Initial ...

Page 70

... Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter ATtiny2313A/4313 70 “Pinout ATtiny2313A/4313” on page “Register Description” on page 81. Count Clear ...

Page 71

The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare Registers (OCR0A and ...

Page 72

... WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (see Figure 11-3 ATtiny2313A/4313 72 Increment or decrement TCNT0 by 1. Select between increment and decrement. ...

Page 73

Figure 11-3. Output Compare Unit, Block Diagram The OCR0x Registers are double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou- ble buffering is ...

Page 74

... The port override function is independent of the Waveform Generation mode. The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. ATtiny2313A/4313 74 COMnx1 Waveform ...

Page 75

Compare Output Mode and Waveform Generation The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes. For all modes, setting the COM0x1 tells the Waveform Generator that no action on the OC0x Register ...

Page 76

... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast ATtiny2313A/4313 76 1 ...

Page 77

PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com- pare Matches between OCR0x and TCNT0. Figure 11-6. Fast PWM ...

Page 78

... In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to ATtiny2313A/4313 78 11-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating ...

Page 79

OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available for the OC0B pin (See visible on the port pin if the data direction for the port pin is ...

Page 80

... PWM mode where OCR0A is TOP. Figure 11-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk I/O TCNTn (CTC) OCRnx OCFnx ATtiny2313A/4313 80 I/O Tn /8) MAX - 1 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) ...

Page 81

Register Description 11.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x30 (0x50) Read/Write Initial Value • Bits 7:6 – COM0A1:0: Compare Match Output A Mode These bits control the Output Compare pin (OC0A) behavior. If one or both of ...

Page 82

... Table 11-6 mode. Table 11-6. COM0B1 Note: ATtiny2313A/4313 82 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase cor- Compare Output Mode, Phase Correct PWM Mode COM0A0 Description 0 Normal port operation, OC0A disconnected. WGM02 = 0: Normal Port Operation, OC0A Disconnected. ...

Page 83

... Note: • Bits 3, 2 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...

Page 84

... OCR0B as TOP. The FOC0B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the • Bits 2:0 – CS02:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter ...

Page 85

Table 11-9. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

Page 86

... Initial Value • Bit 4 – Res: Reserved Bit This bit is reserved bit in the ATtiny2313A/4313 and will always read as zero. • Bit 2 – OCIE0B: Timer/Counter0 Output Compare Match B Interrupt Enable When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the Timer/Counter Compare Match B interrupt is enabled ...

Page 87

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page • Bit 0 – OCF0A: Output Compare Flag 0 A The OCF0A bit is set when a Compare Match occurs ...

Page 88

... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the Figure 12-1. 16-bit Timer/Counter Block Diagram Note: ATtiny2313A/4313 88 “Pinout ATtiny2313A/4313” on page “Register Description” on page Count Clear Control Logic Direction ...

Page 89

Most register and bit references in this section are written in general form. A lower case “n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit channel. However, when using the register or bit defines ...

Page 90

... The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 12-2 Figure 12-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear ATtiny2313A/4313 90 “Timer/Counter0 and Timer/Counter1 Prescalers” on page shows a block diagram of the counter and its surroundings. DATA BUS (8-bit) TEMP (8-bit) ...

Page 91

TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) con- taining the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. The TCNT1H Register can only ...

Page 92

... Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register (ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag must therefore be cleared after the change. ATtiny2313A/4313 92 DATA BUS TEMP (8-bit) ...

Page 93

Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled using the same technique as for the T1 pin identical. However, when the noise canceler is enabled, additional logic is inserted before the edge detector, ...

Page 94

... Then when the low byte (OCR1xL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare Register in the same system clock cycle. ATtiny2313A/4313 94 shows a block diagram of the Output Compare unit. The small “n” in the register and ...

Page 95

For more information of how to access the 16-bit registers refer to on page 12.6.1 Force Output Compare In non-PWM Waveform Generation modes, the match output of the comparator can be forced by writing a one to the Force Output ...

Page 96

... For non-PWM modes, the action can be forced to have immediate effect by using the FOC1x strobe bits. 12.8 Modes of Operation The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output ATtiny2313A/4313 96 Waveform D Generator D ...

Page 97

The Compare Output mode bits do not affect the counting sequence, while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM out- put generated should be inverted or not (inverted or non-inverted PWM). ...

Page 98

... PWM modes that use dual-slope operation. This high fre- quency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capaci- tors), hence reduces total system cost. ATtiny2313A/4313 ...

Page 99

The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the max- imum resolution is 16-bit ...

Page 100

... However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to ATtiny2313A/4313 100 Table 12-2 on page f ...

Page 101

OCR1A set to MAX). The PWM resolu- tion in bits can be calculated by using the following equation: In phase correct PWM mode the counter is incremented until the counter value ...

Page 102

... The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated using the following equation: ATtiny2313A/4313 102 f = ...

Page 103

In phase and frequency correct PWM mode the counter is incremented until the counter value matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The counter has then reached the TOP and ...

Page 104

... OCR1x Register is updated with the OCR1x buffer value (only for modes utilizing double buffering). Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling (clk TCNTn OCRnx OCFnx Figure 12-11 ATtiny2313A/4313 104 f OCnxPFCPWM Figure 12-10 clk I/O clk ...

Page 105

Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f Figure 12-12 on page 105 using phase and frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams will be the same, but TOP should ...

Page 106

... 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low byte must be read before the high byte. The following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. The same principle can be used directly for accessing ATtiny2313A/4313 106 clk I/O ...

Page 107

OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit access. Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to ...

Page 108

... Save global interrupt flag */ sreg = SREG; /* Disable interrupts */ __disable_interrupt(); /* Read TCNT1 into TCNT1; /* Restore global interrupt flag */ SREG = sreg; return i; } Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair. ATtiny2313A/4313 108 (1) (1) 1. See “Code Examples” on page 6. 8246A–AVR–11/09 ...

Page 109

The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...

Page 110

... When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is depen- dent of the WGM13:0 bits setting. WGM13:0 bits are set to a Normal or a CTC mode (non-PWM). Table 12-2. COM1A1/COM1B1 Table 12-3 PWM mode. Table 12-3. COM1A1/COM1B1 Note: ATtiny2313A/4313 110 COM1A1 COM1A0 COM1B1 COM1B0 ...

Page 111

Table 12-4 correct or the phase and frequency correct, PWM mode. Table 12-4. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of ...

Page 112

... When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. ATtiny2313A/4313 112 (1) WGM10 ...

Page 113

When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Cap- ture function is disabled. • Bit 5 – Reserved ...

Page 114

... CPU writes to these registers, the access is performed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other 16- bit registers. 12.11.7 ICR1H and ICR1L – Input Capture Register 1 Bit 0x25 (0x45) 0x24 (0x44) Read/Write Initial Value ATtiny2313A/4313 114 TCNT1[15:8] TCNT1[7:0] R/W R/W ...

Page 115

The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture can be used for defining the counter TOP value. ...

Page 116

... WGM13 used as the TOP value, the ICF1 flag is set when the coun- ter reaches the TOP value. ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively, ICF1 can be cleared by writing a logic one to its bit location. ATtiny2313A/4313 116 8246A–AVR–11/09 ...

Page 117

Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.1 Internal Clock Source The Timer/Counter can be clocked directly ...

Page 118

... Initial Value • Bits 7..1 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and will always read as zero. • Bit 0 – PSR10: Prescaler Reset Timer/Counter1 and Timer/Counter0 When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware ...

Page 119

USART 14.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...

Page 120

... Register. When using synchronous mode (UMSEL = 1), the Data Direction Register for the XCK pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave mode). The XCK pin is only active when using synchronous mode. Figure 14-2 ATtiny2313A/4313 120 shows a block diagram of the clock generation logic. Figure 14-1) if the Buffer Registers 8246A– ...

Page 121

Figure 14-2. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 14.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description ...

Page 122

... CPU clock period delay and therefore the maximum external XCK clock frequency is limited by the following equation: Note that f add some margin to avoid possible loss of data due to frequency variations. ATtiny2313A/4313 122 Equations for Calculating Baud Rate Register Setting Equation for Calculating ...

Page 123

Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...

Page 124

... Transmitter has completed all transfers, and the RXC flag can be used to check that there are no unread data in the receive buffer. Note that the TXC flag must be cleared before each transmission (before UDR is written used for this purpose. ATtiny2313A/4313 124 Data bits (0 to 8). ...

Page 125

The following simple USART initialization code examples show one assembly and one C func- tion that are equal in functionality. The examples assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. The baud rate is given ...

Page 126

... UDR = data; } Note: The function simply waits for the transmit buffer to be empty by checking the UDRE flag, before loading it with new data to be transmitted. If the Data Register Empty interrupt is utilized, the interrupt routine writes the data into the buffer. ATtiny2313A/4313 126 (1) UDR,r16 (1) ; ...

Page 127

Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The following ...

Page 128

... The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo- ing and pending transmissions are completed, i.e., when the Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD pin. ATtiny2313A/4313 128 8246A–AVR–11/09 ...

Page 129

Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Regis- ter to one. When the Receiver is enabled, the normal pin operation of the RxD pin is ...

Page 130

... UDR error, return - status & (1<<FE)|(1<<DOR)|(1<<UPE Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); } Note: ATtiny2313A/4313 130 (1) r18, UCSRA r17, UCSRB r16, UDR r17, HIGH(-1) r16, LOW(-1) r17 (1) ...

Page 131

The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive buffer utilization since the buffer location read will be free to accept new data as early ...

Page 132

... Asynchronous Clock Recovery The clock recovery logic synchronizes internal clock to the incoming serial frames. illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times ATtiny2313A/4313 132 (1) r16, UDR (1) 1. See “ ...

Page 133

Normal mode, and eight times the baud rate for Double Speed mode. The hor- izontal arrows illustrate the synchronization variation due to the sampling process. Note the larger time variation when using the Double Speed mode ...

Page 134

... The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow Table 14-2 that Normal Speed mode has higher toleration of baud rate variations. ATtiny2313A/4313 134 shows the sampling of the stop bit and the earliest possible beginning of the start bit RxD ...

Page 135

Table 14-2. # (Data+Parity Bit) Table 14-3. # (Data+Parity Bit) The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible ...

Page 136

... I/O address referred to as USART Data Register or UDR. The Transmit Data Buffer Reg- ister (TXB) will be the destination for data written to the UDR Register location. Reading the UDR Register location will return the contents of the Receive Data Buffer Register (RXB). ATtiny2313A/4313 136 7 ...

Page 137

For 5-, 6-, or 7-bit characters the upper unused bits will be ignored by the Transmitter and set to zero by the Receiver. The transmit buffer can only be written when the UDRE flag in the UCSRA Register is set. ...

Page 138

... Transmit Shift Register and Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter will no longer override the TxD port. ATtiny2313A/4313 138 “Multi-processor Communication Mode” on page ...

Page 139

Bit 2 – UCSZ2: Character Size The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the number of data bits (Char- acter SiZe frame the Receiver and Transmitter use. • Bit 1 – RXB8: Receive ...

Page 140

... Table 14-8. UCPOL 0 1 14.10.5 UBRRL and UBRRH – USART Baud Rate Registers Bit 0x02 (0x22) 0x09 (0x29) Bit Read/Write Initial Value ATtiny2313A/4313 140 USBS Bit Settings USBS Stop Bit(s) 0 1-bit 1 2-bit UCSZ Bits Settings UCSZ1 UCSZ0 0 ...

Page 141

Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero when UBRRH is written. • Bit 11:0 – UBRR11:0: USART Baud Rate Register This is ...

Page 142

... Max. 230.4 kbps 460.8 kbps 1. UBRR = 0, Error = 0.0% ATtiny2313A/4313 142 f = 4.0000 MHz osc U2X = 0 U2X = 1 Error UBRR Error UBRR 0.0% 103 0.2% 207 0.0% 51 0.2% 103 0.0% 25 0.2% 51 0. ...

Page 143

Table 14-11. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 ...

Page 144

... Table 14-12. Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud Rate (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M (1) Max. 1. ATtiny2313A/4313 144 (Continued) U2X = 0 UBRR Error 416 -0.1% 207 0.2% 103 0.2% 68 0.6% 51 0.2% 34 -0. ...

Page 145

USART in SPI Mode 15.1 Features • Full Duplex, Three-wire Synchronous Data Transfer • Master Operation • Supports all four SPI Modes of Operation (Mode and 3) • LSB First or MSB First Data Transfer (Configurable ...

Page 146

... The UCPOL and UCPHA functionality is summarized in ongoing communication for both the Receiver and Transmitter. Table 15-2. UCPOL Figure 15-1. UCPHA and UCPOL data transfer timing diagrams. ATtiny2313A/4313 146 Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud Rate BAUD = ---------------------------------- - ( 2 UBRR 1 ...

Page 147

Frame Formats A serial frame for the MSPIM is defined to be one character of 8 data bits. The USART in MSPIM mode has two valid frame formats: • 8-bit data with MSB first • 8-bit data with LSB ...

Page 148

... UCSRC = (1<<UMSEL1)|(1<<UMSEL0)|(0<<UCPHA)|(0<<UCPOL); /* Enable receiver and transmitter. */ UCSRB = (1<<RXEN)|(1<<TXEN); /* Set baud rate IMPORTANT: The Baud Rate must be set after the transmitter is enabled */ UBRR = baud; } Note: ATtiny2313A/4313 148 (1) (1) 1. See ”Code Examples” on page 6. 8246A–AVR–11/09 ...

Page 149

Data Transfer Using the USART in MSPI mode requires the Transmitter to be enabled, i.e. the TXEN bit in the UCSRB register is set to one. When the Transmitter is enabled, the normal port operation of the TxD pin ...

Page 150

... USART operation. However, the receiver error status flags (FE, DOR, and PE) are not in use and is always read as zero. 15.6.2 Disabling the Transmitter or Receiver The disabling of the transmitter or receiver in USART in MSPIM mode is identical in function to the normal USART operation. ATtiny2313A/4313 150 (1) (1) 1. See “Code Examples” on page 6. 8246A–AVR–11/09 ...

Page 151

AVR USART MSPIM vs. AVR SPI The USART in MSPIM mode is fully compatible with the AVR SPI regarding: • Master mode timing diagram. • The UCPOL bit functionality is identical to the SPI CPOL bit. • The UCPHA ...

Page 152

... Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one enables interrupt on the RXC Flag. A USART Receive Complete interrupt will be generated only if the RXCIE bit is written to one, the Global Interrupt Flag in SREG is writ- ten to one and the RXC bit in UCSRA is set. ATtiny2313A/4313 152 7 6 ...

Page 153

Bit 6 – TXCIE: TX Complete Interrupt Enable Writing this bit to one enables interrupt on the TXC Flag. A USART Transmit Complete interrupt will be generated only if the TXCIE bit is written to one, the Global Interrupt ...

Page 154

... UBRRL and UBRRH – USART MSPIM Baud Rate Registers The function and bit description of the baud rate registers in MSPI mode is identical to normal USART operation. See “UBRRL and UBRRH – USART Baud Rate Registers” on page 140. ATtiny2313A/4313 154 8246A–AVR–11/09 ...

Page 155

... The most significant bit of the USI Data Register is connected to one of two output pins (depend- ing on the mode configuration, see latch between the output of the USI Data Register and the output pin, which delays the change 8246A–AVR–11/09 “Pinout ATtiny2313A/4313” on page “Register Description” on page 3 2 ...

Page 156

... The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master device software by toggling the USCK pin via the PORTA register or by writing a one to bit USITC bit in USICR. ATtiny2313A/4313 156 Bit7 Bit6 ...

Page 157

Figure 16-3. Three-wire Mode, Timing Diagram CYCLE USCK USCK DO DI The three-wire mode timing is shown in erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The USCK timing is shown for ...

Page 158

... The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC strobe, and toggle USCK. The loop is repeated 16 times. The following code demonstrates how to use the USI as an SPI master with maximum speed ( SCK CK SPITransfer_Fast: ret ATtiny2313A/4313 158 out USICR,r17 in r16, USISR sbrs r16, USIOIF rjmp ...

Page 159

SPI Slave Operation Example The following code demonstrates how to use the USI module as a SPI Slave: init: ... SlaveSPITransfer: SlaveSPITransfer_loop: The code is size optimized using only eight instructions (plus return). The code example assumes that the ...

Page 160

... In addition, the start detector will hold the SCL line low after the master has forced a negative edge on this line (B). This allows the slave to wake up from sleep or complete other tasks before setting up the USI Data Register to receive the address. This is done by clearing the start condition flag and resetting the counter. ATtiny2313A/4313 160 Bit7 Bit6 ...

Page 161

The master set the first bit to be transferred and releases the SCL line (C). The slave samples the data and shifts it into the USI Data Register at the positive edge of the SCL clock. 4. After eight ...

Page 162

... These bits set the type of wire mode to be used, as shown in Basically, only the function of the outputs are affected by these bits. Data and clock inputs are not affected by the mode selected and will always have the same function. The counter and USI ATtiny2313A/4313 162 7 ...

Page 163

Data Register can therefore be clocked externally and data input sampled, even when outputs are disabled. Table 16-1. USIWM1 Note: • Bit 3:2 – USICS1:0: Clock Source Select These bits set the clock source for the ...

Page 164

... When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has been detected. When three-wire mode or output disable mode has been selected any edge on the SCK pin will set the flag. ATtiny2313A/4313 164 shows the relationship between the USICS1:0 and USICLK setting and clock source ...

Page 165

If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener- ated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit. Clearing ...

Page 166

... USI less time critical and gives the CPU more time to handle other pro- gram tasks. USI flags as set similarly as when reading the USIDR register. The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has been completed. ATtiny2313A/4313 166 7 6 ...

Page 167

Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...

Page 168

... PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ- ten logic one to reduce power consumption in the digital input buffer. ATtiny2313A/4313 168 Table 17-1 ...

Page 169

On-chip Debug System 18.1 Features • Complete Program Flow Control • Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...

Page 170

... Also, clock frequencies below 100 kHz may cause communication problems. A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should be disabled when debugWire is not used. ATtiny2313A/4313 170 will not work. CC ® ...

Page 171

Register Description The following section describes the registers used with the debugWire. 18.6.1 DWDR – debugWire Data Register Bit Read/Write Initial Value The DWDR Register provides a communication channel from the running program in the MCU to the debugger. ...

Page 172

... SPMCSR also erased after a system reset. Note that it is not possible to write more than one time to each address without erasing the temporary buffer. Note: ATtiny2313A/4313 172 The CPU is halted during the Page Erase operation. If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be lost. 8246A– ...

Page 173

Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...

Page 174

... Read the FLB from the LPM destination register. If successful, the contents of the destination register are as follows. Bit Rd Refer to ATtiny2313A/4313 174 Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro- grammed, will be read as one. 7 ...

Page 175

To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and repeat the procedure above. If successful, the contents of the destination register are as follows. Bit Rd Refer to To read the Fuse ...

Page 176

... Initial Value • Bits 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny2313A/4313 and always read as zero. • Bit 5 – RSIG: Read Device Signature Imprint Table Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in ...

Page 177

See details. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be cleared and the data will ...

Page 178

... This section describes the different methods for programming ATtiny2313A/4313 memories. 20.1 Program And Data Memory Lock Bits The ATtiny2313A/4313 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in erased to “1” with the Chip Erase command. ...

Page 179

... Fuse Bits The ATtiny2313A/4313 has three Fuse bytes. briefly the functionality of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 20-3. Fuse Extended ...

Page 180

... Byte addresses are used when the device itself reads the data with the LPM command. External programming devices must use word addresses. Table 20-6. Word Address 0x00 0x01 0x02 ATtiny2313A/4313 180 Fuse Low Byte Bit No Description 7 Divide clock ...

Page 181

... Calibration Byte The signature area of the ATtiny2313A/4313 contains two bytes of calibration data for the inter- nal oscillator. The calibration data in the high byte of address 0x00 is for use with the oscillator set to 8.0 MHz operation. During reset, this byte is automatically written into the OSCCAL regis- ter to ensure correct frequency of the oscillator ...

Page 182

... Parallel Programming Parameters, Pin Mapping, and Commands This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory, Memory Lock bits, and Fuse bits in the ATtiny2313A/4313. Pulses are assumed least 250 ns unless otherwise noted. 20.5.1 Signal Names ...

Page 183

Table 20-10. Pin Values Used to Enter Programming Mode Table 20-11. XA1 and XA0 Coding XA1 When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 20-12. ...

Page 184

... Wait until RDY/BSY goes high before loading a new command. 20.6.4 Programming the Flash The Flash is organized in pages, see the program data is latched into a page buffer. This allows one page of program data to be pro- ATtiny2313A/4313 184 is unable to fulfill the requirements listed above, the following alterna- CC Table 20-10 on page 183 to 0V ...

Page 185

The following procedure describes how to program the entire Flash memory: A. Load Command “Write Flash” 1. Set XA1, XA0 to “10”. This enables command loading. 2. Set BS1 to “0”. 3. Set DATA to “0001 0000”. This ...

Page 186

... EEPROM, the program data is latched into a page buffer. This allows one page of data to be programmed simultaneously. The programming algorithm for the EEPROM data memory is as follows (refer to Data loading Load Command “0001 0001” Load Address High Byte (0x00 - 0xFF). ATtiny2313A/4313 186 PCMSB PROGRAM PCPAGE COUNTER ...

Page 187

B: Load Address Low Byte (0x00 - 0xFF Load Data (0x00 - 0xFF). J: Repeat 3 through 4 until the entire buffer is filled. K: Program EEPROM page 1. Set BS1 to “0”. 2. Give WR a ...

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... Give WR a negative pulse and wait for RDY/BSY to go high Set BS2 to “0”. This selects low data byte. Figure 20-5. Programming the FUSES Waveforms RDY/BSY RESET +12V ATtiny2313A/4313 188 for details on Command and Data loading): for details on Command and Data loading): for details on Command and Data loading): ...

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Programming the Lock Bits The algorithm for programming the Lock bits is as follows (refer to page 184 1. A: Load Command “0010 0000” Load Data Low Byte. Bit n = “0” programs the Lock bit. If ...

Page 190

... Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low: > 2 CPU clock cycles for f High: > 2 CPU clock cycles for f ATtiny2313A/4313 190 for details on Command and Address loading): MOSI ...

Page 191

... Table 20-13. Pin Mapping Serial Programming 20.8.1 Serial Programming Algorithm When writing serial data to the ATtiny2313A/4313, data is clocked on the rising edge of SCK. When reading data from the ATtiny2313A/4313, data is clocked on the falling edge of SCK. See Figure To program and verify the ATtiny2313A/4313 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in 1 ...

Page 192

... Turn V Table 20-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM t WD_ERASE t WD_FUSE ATtiny2313A/4313 192 Table 20-14 on page 192 chip erased device, no 0xFF in the data power off. CC Minimum Wait Delay 4.5 ms 4.0 ms 9.0 ms 4.5 ms 8246A–AVR–11/09 ...

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Serial Programming Instruction Set Table 20-15. Serial Programming Instruction Set Instruction Byte 1 Programming Enable 1010 1100 Chip Erase 1010 1100 Read Program Memory 0010 H000 Load Program Memory Page 0100 H000 Write Program Memory Page 0100 1100 Read ...

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... Read Extended Fuse Bits 0101 0000 Read Calibration Byte 0011 1000 Poll RDY/BSY 1111 0000 Note address high bits address low bits Low byte High Byte data out data in don’t care ATtiny2313A/4313 194 Instruction Format Byte 2 Byte 3 Byte4 0000 1000 xxxx xxxx ...

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Electrical Characteristics 21.1 Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on any Pin except RESET with respect to Ground ................................-0. Voltage on RESET with respect to Ground......-0.5V to +13.0V ...

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... I/O drive. 8. BOD Disabled. 21.3 Speed Grades The maximum operating frequency of the device depends on V relationship between maximum frequency and V Figure 21-1. Maximum Frequency vs. V ATtiny2313A/4313 196 Condition Min. (7) Active 1MHz ...

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Clock Characteristics 21.4.1 Calibrated Internal RC Oscillator Accuracy It is possible to manually calibrate the internal oscillator to be more accurate than default factory calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics ...

Page 198

... Table 21-4. Symbol V POR V POA SR ON Notes: 21.5.2 Brown-Out Detection Table 21-5. BODLEVEL [1:0] Fuses Note: ATtiny2313A/4313 198 Reset, Brown-out, and Internal Voltage Characteristics Parameter RESET Pin Threshold Voltage Minimum pulse width on V (1)(2) RESET Pin Brown-out Detector (2) Hysteresis Min Pulse Width on ...

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Analog Comparator Characteristics Table 21-6. Analog Comparator Characteristics, T Symbol Parameter V Input Offset Voltage ACIO I Input Leakage Current ACLK Analog Propagation Delay (from saturation to slight overdrive) t ACPD Analog Propagation Delay (large step change) t Digital ...

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... WLRH_CE t XLOL t BVDV t OLDV t OHDZ Notes: ATtiny2313A/4313 200 Parallel Programming Characteristics, V Parameter Programming Enable Voltage Programming Enable Current Data and Control Valid before XTAL1 High XTAL1 Low to XTAL1 High XTAL1 Pulse Width High Data and Control Hold after XTAL1 Low XTAL1 Low to WR Low ...

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