ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet - Page 23

• Manufacturer Part Number: ATTINY2313A-PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ATtiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.5.4
5.5.5
5.5.6
8246A–AVR–11/09
GPIOR2 – General Purpose I/O Register 2
GPIOR1 – General Purpose I/O Register 1
GPIOR0 – General Purpose I/O Register 0
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the
selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.
When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.
The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no
EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared
by hardware. When EEPE has been set, the CPU is halted for two cycles before the next
instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-
rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed. The user should poll the EEPE bit before starting the read opera-
tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change
the EEAR Register.
Bit
0x15 (0x35)
Read/Write
Initial Value
Bit
0x14 (0x34)
Read/Write
Initial Value
Bit
0x13 (0x33)
Read/Write
Initial Value
MSB
MSB
MSB
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
R/W
R/W
R/W
1
0
1
0
1
0
LSB
R/W
LSB
R/W
LSB
R/W
0
0
0
0
0
0
GPIOR2
GPIOR1
GPIOR0
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