ATTINY2313A-PU Atmel, ATTINY2313A-PU Datasheet - Page 201

• Manufacturer Part Number: ATTINY2313A-PU
• Description: IC MCU AVR 2K FLASH 20MHZ 20DIP
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY2313A-PU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Processor Series: ATTINY2x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• Controller Family/series: ATtiny
• No. Of I/o's: 18
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 128Byte
• Cpu Speed: 20MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8246A–AVR–11/09
Figure 21-3. Parallel Programming Timing, Including some General Timing Requirements
Figure 21-4. Parallel Programming Timing, Loading Sequence with Timing Requirements
Note:
Figure 21-5. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Note:
XTAL1
DATA
(DATA, XA0/1, BS1, BS2)
BS1
XA0
XA1
OE
PAGEL
XTAL1
1. The timing requirements shown in
1. The timing requirements shown in
DATA
BS1
XA0
XA1
ing operation.
ing operation.
Data & Contol
Timing Requirements
RDY/BSY
ADDR0 (Low Byte)
LOAD ADDRESS
PAGEL
(LOW BYTE)
XTAL1
ADDR0 (Low Byte)
LOAD ADDRESS
(LOW BYTE)
WR
t
XLOL
t
OLDV
t
t
BVPH
DVXH
(1)
(LOW BYTE)
LOAD DATA
DATA (Low Byte)
t
t
XHXL
PHPL
DATA (Low Byte)
READ DATA
(LOW BYTE)
Figure 21-3
Figure 21-3
t
t
t
t
t
XLXH
XLDX
XLWL
PLBX
PLWL
t
BVDV
(i.e., t
(i.e., t
t
(HIGH BYTE)
BVWL
LOAD DATA
DATA (High Byte)
DVXH
DVXH
(HIGH BYTE)
READ DATA
t
t
DATA (High Byte)
XLPH
WLWH
WLRL
LOAD DATA
, t
, t
XHXL
XHXL
, and t
, and t
t
PLXH
t
OHDZ
t
WLBX
XLDX
XLDX
LOAD ADDRESS
LOAD ADDRESS
(LOW BYTE)
(LOW BYTE)
ADDR1 (Low Byte)
) also apply to read-
) also apply to load-
ADDR1 (Low Byte)
t
WLRH
(1)
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