MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 81
![EVAL BOARD FOR MC56F83X](/photos/9/23/92375/mc56f8367evme_sml.jpg)
MC56F8367EVME
Manufacturer Part Number
MC56F8367EVME
Description
EVAL BOARD FOR MC56F83X
Manufacturer
Freescale Semiconductor
Type
DSPr
Specifications of MC56F8367EVME
Contents
Module and Misc Hardware
Processor To Be Evaluated
MC56F8145-67 and MC56F8345-67
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F83xx
Rohs Compliant
Yes
For Use With/related Products
MC56F83x5, MC56F83x6, MC56F83x7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part 5 Interrupt Controller (ITCN)
5.1 Introduction
The Interrupt Controller (ITCN) module is used to arbitrate between various interrupt requests (IRQs), to
signal to the 56800E core when an interrupt of sufficient priority exists, and what address to jump in order
to service this interrupt.
5.2 Features
The ITCN module design includes these distinctive features:
For further information, see
5.3 Functional Description
The Interrupt Controller is a slave on the IPBus. It contains registers allowing each of the 86 interrupt
sources to be set to one of four priority levels, excluding certain interrupts of fixed priority. Next, all of
the interrupt requests of a given level are priority encoded to determine the lowest numerical value of the
active interrupt requests for that level. Within a given priority level, 0 is the highest priority, while number
85 is the lowest.
5.3.1
Once the ITCN has determined that an interrupt is to be serviced and which interrupt has the highest
priority, an interrupt vector address is generated. Normal interrupt handling concatenates the VBA and the
vector number to determine the vector address. In this way, an offset is generated into the vector table for
each interrupt.
5.3.2
Interrupt exceptions may be nested to allow an IRQ of higher priority than the current exception to be
serviced. The following tables define the nesting requirements for each priority level.
Freescale Semiconductor
Preliminary
•
•
•
•
Programmable priority levels for each IRQ
Two programmable Fast Interrupts
Notification to SIM module to restart clocks out of Wait and Stop modes
Drives initial address on the address bus after reset
1. Core status register bits indicating current interrupt mask within the core.
Normal Interrupt Handling
Interrupt Nesting
SR[9]
0
0
1
1
1
Table
Table 5-1 Interrupt Mask Bit Definition
SR[8]
0
1
0
1
4-5, Interrupt Vector Table Contents.
1
56F8367 Technical Data, Rev. 8
Priorities 0, 1, 2, 3
Priorities 1, 2, 3
Priorities 2, 3
Priority 3
Permitted Exceptions
None
Priority 0
Priorities 0, 1
Priorities 0, 1, 2
Masked Exceptions
Introduction
81
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