MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 4

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Part 1: Overview. . . . . . . . . . . . . . . . . . . . . . . 5
Part 2: Signal/Connection Descriptions . . . 15
Part 3: On-Chip Clock Synthesis (OCCS) . 39
Part 4: Memory Operating Modes (MEM). . 41
Part 5: Interrupt Controller (ITCN) . . . . . . . . 81
Part 6: System Integration Module (SIM) . 111
Part 7: Security Features . . . . . . . . . . . . . . 129
4
1.1. 56F8367/56F8167 Features . . . . . . . . . . . . . 5
1.2. Device Description . . . . . . . . . . . . . . . . . . . . 7
1.3. Award-Winning Development Environment . 9
1.4. Architecture Block Diagram . . . . . . . . . . . . . 10
1.5. Product Documentation . . . . . . . . . . . . . . . . 14
1.6. Data Sheet Conventions . . . . . . . . . . . . . . . 14
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2. Signal Pins . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.2. External Clock Operation . . . . . . . . . . . . . . 39
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2. Program Map . . . . . . . . . . . . . . . . . . . . . . . 42
4.3. Interrupt Vector Table . . . . . . . . . . . . . . . . . 43
4.4. Data Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.5. Flash Memory Map . . . . . . . . . . . . . . . . . . . 47
4.6. EOnCE Memory Map . . . . . . . . . . . . . . . . . 49
4.7. Peripheral Memory Mapped Registers . . . . 49
4.8. Factory Programmed Memory. . . . . . . . . . . 80
5.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
5.3. Functional Description . . . . . . . . . . . . . . . . . 81
5.4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 83
5.5. Operating Modes . . . . . . . . . . . . . . . . . . . . . 83
5.6. Register Descriptions . . . . . . . . . . . . . . . . . 84
5.7. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . 111
6.3. Operating Modes . . . . . . . . . . . . . . . . . . . 112
6.4. Operating Mode Register . . . . . . . . . . . . . 112
6.5. Register Descriptions . . . . . . . . . . . . . . . . 113
6.6. Clock Generation Overview . . . . . . . . . . . 127
6.7. Power Down Modes Overview . . . . . . . . . 128
6.8. Stop and Wait Mode Disable Function . . . 128
6.9. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
7.1. Operation with Security Enabled . . . . . . . . 129
7.2. Flash Access Blocking Mechanisms . . . . 130
Table of Contents
56F8367 Technical Data, Rev. 8
Part 8: General Purpose Input/Output
Part 9: Joint Test Action Group (JTAG) . . 137
Part 10: Specifications. . . . . . . . . . . . . . . . 138
Part 11: Packaging . . . . . . . . . . . . . . . . . . 166
Part 12: Design Considerations . . . . . . . . 177
Part 13: Ordering Information . . . . . . . . . . 180
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . 132
8.2. Memory Maps . . . . . . . . . . . . . . . . . . . . . . 132
8.3. Configuration. . . . . . . . . . . . . . . . . . . . . . . . 133
9.1. 56F8367 Information. . . . . . . . . . . . . . . . . 137
10.1. General Characteristics . . . . . . . . . . . . . . 138
10.2. DC Electrical Characteristics. . . . . . . . . . 142
10.3. AC Electrical Characteristics. . . . . . . . . . 146
10.4. Flash Memory Characteristics. . . . . . . . . 146
10.5. External Clock Operation Timing . . . . . . 147
10.6. Phase Locked Loop Timing. . . . . . . . . . . 147
10.7. Crystal Oscillator Timing . . . . . . . . . . . . . 148
10.8. External Memory Interface Timing . . . . . . 148
10.9. Reset, Stop, Wait, Mode Select, and
10.10. Serial Peripheral Interface
10.11. Quad Timer Timing . . . . . . . . . . . . . . . . 157
10.12. Quadrature Decoder Timing . . . . . . . . . . 157
10.13. Serial Communication Interface
10.14. Controller Area Network (CAN) Timing . 159
10.15. JTAG Timing . . . . . . . . . . . . . . . . . . . . . 159
10.16. Analog-to-Digital Converter
10.17. Equivalent Circuit for ADC Inputs . . . . . 164
10.18. Power Consumption . . . . . . . . . . . . . . . 164
11.1. 56F8367 Package and Pin-Out
11.2. 56F8167 Package and Pin-Out
12.1. Thermal Design Considerations . . . . . . . 177
12.2. Electrical Design Considerations . . . . . . 178
12.3. Power Distribution and I/O Ring
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . 132
Interrupt Timing . . . . . . . . . . . . . 151
(SPI) Timing . . . . . . . . . . . . . . . . . 153
(SCI) Timing . . . . . . . . . . . . . . . . 158
(ADC) Parameters . . . . . . . . . . . 161
Information . . . . . . . . . . . . . . . . . . 166
Information . . . . . . . . . . . . . . . . . 173
Implementation . . . . . . . . . . . . . . 179
Freescale Semiconductor
Preliminary