MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 111
MC56F8367EVME
Manufacturer Part Number
MC56F8367EVME
Description
EVAL BOARD FOR MC56F83X
Manufacturer
Freescale Semiconductor
Type
DSPr
Specifications of MC56F8367EVME
Contents
Module and Misc Hardware
Processor To Be Evaluated
MC56F8145-67 and MC56F8345-67
Data Bus Width
16 bit
Interface Type
RS-232
Silicon Manufacturer
Freescale
Core Architecture
56800/E
Core Sub-architecture
56800/E
Silicon Core Number
MC56F
Silicon Family Name
MC56F83xx
Rohs Compliant
Yes
For Use With/related Products
MC56F83x5, MC56F83x6, MC56F83x7
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Part 6 System Integration Module (SIM)
6.1 Overview
The SIM module is a system catchall for the glue logic that ties together the system-on-chip. It controls
distribution of resets and clocks and provides a number of control features. The system integration module
is responsible for the following functions:
These are discussed in more detail in the sections that follow.
6.2 Features
The SIM has the following features:
Freescale Semiconductor
Preliminary
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Reset sequencing
Clock generation & distribution
Stop/Wait control
Pull-up Enables for Selected Peripherals
System status registers
Registers for software access to the JTAG ID of the chip
Enforcing Flash security
Flash security feature prevents unauthorized access to code/data contained in on-chip Flash memory
Power-saving clock gating for peripheral
Three power modes (Run, Wait, Stop) to control power utilization
— Stop mode shuts down 56800E core, system clock, peripheral clock, and PLL operation
— Stop mode entry can optionally disable PLL and Oscillator (low power vs. fast restart); must be done
— Wait mode shuts down the 56800E core, and unnecessary system clock operation
— Run mode supports full part operation
Controls to enable/disable the 56800E core WAIT and STOP instructions
Calculates base delay for reset extension based upon POR or RESET operations. Reset delay will be either
3 x 32 clocks for reset, except for POR, which is 2
Controls reset sequencing after reset
Software-initiated reset
Four 16-bit registers reset only by a Power-On Reset usable for general purpose software control
System Control Register
Registers for software access to the JTAG ID of the chip
explicitly
56F8367 Technical Data, Rev. 8
21
clock cycles.
Overview
111
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