MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 75

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Preliminary
FCMB14_CONTROL
FCMB14_ID_HIGH
FCMB14_ID_LOW
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
FCMB14_DATA
FCMB15_CONTROL
FCMB15_ID_HIGH
FCMB15_ID_LOW
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
FCMB15_DATA
FC2MCR
FC2CTL0
FC2CTL1
FC2TMR
FC2MAXMB
FC2IMASK2
FC2RXGMASK_H
FC2RXGMASK_L
FC2RX14MASK_H
FC2RX14MASK_L
Register Acronym
Register Acronym
Table 4-38 FlexCAN Registers Address Map (Continued)
FlexCAN2 is NOT available in the 56F8167 device
FlexCAN is NOT available in the 56F8167 device
Table 4-39 FlexCAN2 Registers Address Map
Address Offset
Address Offset
(FC2_BASE = $00 FA00)
56F8367 Technical Data, Rev. 8
(FC_BASE = $00 F800)
$BC
$BD
$B0
$B2
$B3
$B4
$B5
$B6
$B8
$BA
$BB
$BE
$B1
$B9
$A
$B
$0
$3
$4
$5
$6
$7
$8
$9
Reserved
Message Buffer 14 Control / Status Register
Message Buffer 14 ID High Register
Message Buffer 14 ID Low Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Message Buffer 14 Data Register
Reserved
Message Buffer 15 Control / Status Register
Message Buffer 15 ID High Register
Message Buffer 15 ID Low Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Message Buffer 15 Data Register
Reserved
Module Configuration Register
Reserved
Control Register 0 Register
Control Register 1 Register
Free-Running Timer Register
Maximum Message Buffer Configuration Register
Interrupt Masks 2 Register
Receive Global Mask High Register
Receive Global Mask Low Register
Receive Buffer 14 Mask High Register
Receive Buffer 14 Mask Low Register
Register Description
Register Description
Peripheral Memory Mapped Registers
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