MC56F8367EVME Freescale Semiconductor, MC56F8367EVME Datasheet - Page 43

• Manufacturer Part Number: MC56F8367EVME
• Description: EVAL BOARD FOR MC56F83X
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8367EVME

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8145-67 and MC56F8345-67
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: 56800/E
• Core Sub-architecture: 56800/E
• Silicon Core Number: MC56F
• Silicon Family Name: MC56F83xx
• Rohs Compliant: Yes
• For Use With/related Products: MC56F83x5, MC56F83x6, MC56F83x7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3 Interrupt Vector Table
Table 4-5
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
Freescale Semiconductor
Preliminary
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See Security Features,
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. “EMI_MODE = 0” when EMI_MODE pin is tied to ground at boot up.
4. “EMI_MODE = 1” when EMI_MODE pin is tied to V
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip
6. Not accessible in reset configuration, since the address is above P:$0F FFFF. The higher bit address/GPIO (and/or chip
7. Booting from this external address allows prototyping of the internal Boot Flash.
8. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must
P:$1F FFFF
P:$10 0000
P:$0F FFFF
P:$05 0000
P:$04 FFFF
P:$04 F800
P:$04 F7FF
P:$04 4000
P:$04 3FFF
P:$04 0000
P:$03 FFFF
P:$02 0000
P:$01 FFFF
P:$01 0000
P:$00 FFFF
P:$00 0000
selects) pins must be reconfigured before this external memory is accessible.
selects) pins must be reconfigured before this external memory is accessible.
have its own mass erase.
Begin/End
Address
provides the reset and interrupt priority structure, including on-chip peripherals. The table is
External Program Memory
Boot Flash
32KB
COP Reset Address = 04 0002
Boot Location = 04 0000
Internal Program Flash
256KB
Internal Program Flash
256KB
16-Bit External Address Bus
Mode 0 (MA = 0)
Internal Boot
Internal Boot
Table 4-4 Program Memory Map at Reset
On-Chip Program RAM
8
8
56F8367 Technical Data, Rev. 8
5
Reserved
DD
92KB
4KB
at boot up.
External Program Memory
Boot Flash
32KB
(Not Used for Boot in this Mode)
Internal Program Flash
256KB
Internal Program Flash
128KB
External Program Memory
COP Reset Address = 00 0002
Boot Location = 00 0000
16-Bit External Address Bus
EMI_MODE = 0
2
,
Mode 1
3
5
External Boot
1
(MA = 1)
External Program Memory
External Program Memory
COP Reset Address = 04 0002
Boot Location = 04 0000
20-Bit External Address Bus
Part
7.
EMI_MODE = 1
Interrupt Vector Table
4
7
6
7
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