MCP1631RD-DCPC1 Microchip Technology, MCP1631RD-DCPC1 Datasheet - Page 74
![REF DES BATT CHARG OR LED DRIVER](/photos/28/39/283975/mcp1631rd-dcpc1_sml.jpg)
MCP1631RD-DCPC1
Manufacturer Part Number
MCP1631RD-DCPC1
Description
REF DES BATT CHARG OR LED DRIVER
Manufacturer
Microchip Technology
Datasheets
1.PIC16F616T-ISL.pdf
(214 pages)
2.MCP1631VHVT-330EST.pdf
(34 pages)
3.MCP1631VHVT-330EST.pdf
(32 pages)
Specifications of MCP1631RD-DCPC1
Current - Output / Channel
700mA
Outputs And Type
1, Non-Isolated
Features
Firmware for Li-Ion, NiMH, and NiCd Battery Charger
Voltage - Input
3.5 ~ 16 V
Utilized Ic / Part
MCP1631HV, PIC16F616
Core Chip
MCP1631HV, PIC16F616
Topology
Parallel, Series
Output Current
1A
No. Of Outputs
1
Input Voltage
3.5V To 16V
Dimming Control Type
Analog
Kit Contents
Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Voltage - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- MCP1631VHVT-330EST PDF datasheet #2
- MCP1631VHVT-330EST PDF datasheet #3
- Current page: 74 of 214
- Download datasheet (4Mb)
PIC16F610/616/16HV610/616
9.1
When configuring and using the ADC, the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Results formatting
9.1.1
The ADC can be used to convert both analog and digital
signals. When converting analog signals, the I/O pin
should be configured for analog by setting the associated
TRIS and ANSEL bits. See the corresponding Port
section for more information.
9.1.2
The CHS bits of the ADCON0 register determine which
channel is connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. Refer to Section 9.2
“ADC Operation” for more information.
9.1.3
The VCFG bit of the ADCON0 register provides control
of the positive voltage reference. The positive voltage
reference can be either V
source. The negative voltage reference is always
connected to the ground reference.
TABLE 9-1:
DS41288F-page 74
Legend: Shaded cells are outside of recommended range.
Note 1:
ADC Clock Source
Note:
F
F
F
2:
3:
4:
F
F
F
OSC
OSC
OSC
ADC Configuration
OSC
OSC
OSC
F
ADC Clock Period (T
RC
The F
These values violate the minimum required T
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the F
conversion will be performed during Sleep.
PORT CONFIGURATION
Analog voltages on any pin that is defined
as a digital input may cause the input buf-
fer to conduct excess current.
CHANNEL SELECTION
ADC V
/16
/32
/64
/2
/4
/8
RC
ADC CLOCK PERIOD (T
OLTAGE REFERENCE
source has a typical T
DD
ADCS<2:0>
or an external voltage
AD
000
100
001
101
010
110
x11
)
AD
time of 4 μs for V
AD
) V
2-6 μs
100 ns
200 ns
400 ns
800 ns
20 MHz
1.6 μs
3.2 μs
S
. DEVICE OPERATING FREQUENCIES (V
(1,4)
AD
(2)
(2)
(2)
(2)
time.
DD
9.1.4
The source of the conversion clock is software
selectable via the ADCS bits of the ADCON1 register.
There are seven possible clock options:
• F
• F
• F
• F
• F
• F
• F
The time to complete one bit conversion is defined as
T
as shown in Figure 9-3.
For correct conversion, the appropriate T
must be met. See A/D conversion requirements in
Section 15.0 “Electrical Specifications” for more
information. Table 9-1 gives examples of appropriate
ADC clock selections.
AD
Note:
> 3.0V.
OSC
OSC
OSC
OSC
OSC
OSC
RC
. One full 10-bit conversion requires 11 T
2-6 μs
RC
250 ns
500 ns
Device Frequency (F
1.0 μs
8.0 μs
8 MHz
2.0 μs
4.0 μs
(dedicated internal oscillator)
/2
/4
/8
/16
/32
/64
clock source is only recommended if the
(1,4)
(2)
(3)
(2)
(2)
Unless using the F
system clock frequency will change the
ADC
adversely affect the ADC result.
CONVERSION CLOCK
clock
2-6 μs
16.0 μs
500 ns
1.0 μs
8.0 μs
© 2009 Microchip Technology Inc.
4 MHz
2.0 μs
4.0 μs
OSC
frequency,
(1,4)
(2)
(3)
(2)
(3)
RC
)
, any changes in the
DD
AD
2-6 μs
16.0 μs
32.0 μs
64.0 μs
which
8.0 μs
1 MHz
2.0 μs
4.0 μs
specification
> 3.0V)
AD
(1,4)
periods
(3)
(3)
(3)
(3)
may
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