HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 4

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

3.6
3.7
3.8
3.9
Section 4 Exception Handling
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
3.5.8 System Control Instructions ······················································································59
3.5.9 Short-Format Instructions ·························································································62
Operating Modes ··················································································································62
3.6.1 Minimum Mode ········································································································62
3.6.2 Maximum Mode ········································································································63
Basic Operational Timing ····································································································63
3.7.1 Overview ···················································································································63
3.7.2 On-Chip Memory Access Cycle ···············································································64
3.7.3 Pin States during On-Chip Memory Access ·····························································65
3.7.4 Register Field Access Cycle (Addresses H'FE80 to H'FFFF) ··································66
3.7.5 Pin States during Register Field Access (Addresses H'FE80 to H'FFFF) ················67
3.7.6 External Access Cycle ······························································································ 68
CPU States ···························································································································69
3.8.1 Overview ···················································································································69
3.8.2 Program Execution State ···························································································71
3.8.3 Exception-Handling State ·························································································71
3.8.4 Bus-Released State ····································································································72
3.8.5 Reset State ·················································································································77
3.8.6 Power-Down State ····································································································77
Programming Notes ·············································································································78
3.9.1 Restriction on Address Location ···············································································78
Overview ······························································································································79
4.1.1 Types of Exception Handling and Their Priority ······················································79
4.1.2 Hardware Exception-Handling Sequence ·································································80
4.1.3 Exception Factors and Vector Table ·········································································80
Reset ····································································································································83
4.2.1 Overview ···················································································································83
4.2.2 Reset Sequence ·········································································································83
4.2.3 Stack Pointer Initialization ························································································84
Address Error ·······················································································································87
4.3.1 Illegal Instruction Prefetch ························································································87
4.3.2 Word Data Access at Odd Address ···········································································87
4.3.3 Off-Chip Address Access in Single-Chip Mode ·······················································87
Trace ····································································································································88
Interrupts ······························································································································88
Invalid Instruction ················································································································91
Trap Instructions and Zero Divide ·······················································································91
Cases in Which Exception Handling is Deferred ·································································91
4.8.1 Instructions that Disable Interrupts ···········································································91