HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 232

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

The timer counter can be cleared by an external reset input or by an internal compare-match signal
generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the timer
control register select the method of clearing.
When the timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
The timer counter is initialized to H'00 at a reset and in the standby modes.
11.2.2 Time Constant Registers A and B (TCORA and TCORB)—H'FED2 and H'FED3
Bit
Initial value
Read/Write
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers. When a match is detected, the
corresponding compare-match flag (CMFA or CMFB) is set in the timer control/status register
(TCSR).
The timer output signal (TMO) is controlled by these compare-match signals as specified by
output select bits 1 to 0 (OS1 to OS0) in the timer status/control register (TCSR).
TCORA and TCORB are initialized to H'FF at a reset and in the standby modes.
11.2.3 Timer Control Register (TCR)—H'FED0
Bit
Initial value
Read/Write
The TCR is an 8-bit readable/writable register that selects the clock source and the time at which
the timer counter is cleared, and enables interrupts.
The TCR is initialized to H'00 at a reset and in the standby modes.
CMIEB
R/W
R/W
7
1
7
0
CMIEA
R/W
R/W
6
1
6
0
OVIE
R/W
R/W
5
1
5
0
CCLR1
216
R/W
R/W
4
1
4
0
CCLR0
R/W
R/W
3
1
3
0
CKS2
R/W
R/W
2
1
2
0
CKS1
R/W
R/W
1
1
1
0
CKS0
R/W
R/W
0
1
0
0