HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 204

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HD6435348R

Manufacturer Part Number
HD6435348R
Description
Single-Chip Microcomputer
Manufacturer
Hitachi Semiconductor
Datasheet
Bit
Initial value 0
Read/WriteR/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Table 10-2 Register Configuration (cont)
Channel
3
* Software can write a 0 to clear bits 7 to 4, but cannot write a 1 in these bits.
10.2 Register Descriptions
10.2.1 Free-Running Counter (FRC)—H'FE92, H'FEA2, H'FEB2
Each FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated
from a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and
CKS0) of the timer control register (TCR).
The FRC can be cleared by compare-match A.
When the FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
Because the FRC is a 16-bit register, a temporary register (TEMP) is used when the FRC is
written or read. See section 10.3, “CPU Interface” for details.
The FRCs are initialized to H'0000 at a reset and in the standby modes.
15
Name
Timer control register
Timer control/status register
Free-running counter (High)
Free-running counter (Low)
Output compare register A (High)
Output compare register A (Low)
Output compare register B (High)
Output compare register B (Low)
Input capture register (High)
Input capture register (Low)
14
0
13
0
12
0
11
0
10
0
9
0
187
Abbreviation
TCR
TCSR
FRC (H)
FRC (L)
OCRA (H)
OCRA (L)
OCRB (H)
OCRB (L)
ICR (H)
ICR (L)
8
0
7
0
6
0
5
0
R/W
R/W
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R
R
4
0
Initial
Value
H'00
H'00
H'00
H'00
H'FF
H'FF
H'FF
H'FF
H'00
H'00
3
0
2
0
Address
H'FEB0
H'FEB1
H'FEB2
H'FEB3
H'FEB4
H'FEB5
H'FEB6
H'FEB7
H'FEB8
H'FEB9
1
0
0
0

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