HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 162

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

1. Port 1 Data Direction Register (P1DDR)—H'FE80
Bit
Initial value
Read/Write
P1DDR is an 8-bit register that selects the direction of each pin in port 1. A pin functions as an
output pin if the corresponding bit in P1DDR is set to 1, and as an input pin if the bit is cleared to
0.
P1DDR can be written but not read. An attempt to read this register does not cause an error, but
all bits are read as 1, regardless of their true values.
A reset initializes P1DDR to H'03, so that pins P1
are set for input. In the hardware standby mode, P1DDR is cleared to H'00, stopping the clock
outputs. P1DDR is not initialized in the software standby mode, so if a P1DDR bit is set to 1
when the chip enters the software standby mode, the corresponding pin continues to output the
value in the port 1 data register (or the ø or E clock).
2. Port 1 Data Register (P1DR)—H'FE82
Bit
Initial value
Read/Write
P1DR is an 8-bit register containing the data for pins P1
output pins it reads the value in the P1DR latch, but for input pins, it obtains the pin status
directly.
Note that when pins P1
the contents of P1DR. If the CPU reads Pl
clock values at the current instant.
3. System Control Register 1 (SYSCR1)—H'FEFC
Bit
Initial value
Read/Write
P1
R/W
P1
7
—
—
W
7
DDR P1
0
7
0
7
1
7
1
and P1
IRQ
R/W
R/W
P1
6
W
6
0
6
0
6
0
DDR P1
1
6
E
0
are used for output, they output the clock signals (ø and E), not
IRQ
R/W
R/W
P1
5
W
5
DDR P1
0
5
0
5
0
0
5
E
1
and Pl
NMIEG
145
R/W
R/W
P1
4
W
4
DDR P1
0
4
0
4
0
1
0
4
and P1
(when Pl
7
BRLE
to P1
R/W
R/W
P1
3
0
W
3
0
3
0
3
0
DDR P1
carry clock outputs and the other pins
3
1
DDR = Pl
0
. When the CPU reads P1DR, for
R/W
P1
2
—
W
—
2
DDR P1
0
2
0
2
1
2
0
DDR = 1), it obtains the
P1
1
—
—
—
W
R
1
1
1
1
1
DDR P1
1
P1
0
W
—
—
—
R
0
DDR
1
0
0
1
0