HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 219

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

10.6 Synchronization of Free-Running Timers 1 to 3
10.6.1 Synchronization after a Reset
The three free-running timer channels are synchronized at a reset and remained synchronized
until:
• the clock source is changed;
• FRC contents are rewritten; or
• an FRC is cleared.
After a reset, each free-running counter operates on the ø/4 internal clock source.
10.6.2 Synchronization by Writing to FRCs
When synchronization among free-running timers 1 to 3 is lost, it can be restored by writing to the
free-running counters.
Synchronization on Internal Clock Source: When an internal clock is selected, free-running
timers 1 to 3 can be synchronized by writing data to their free-running counters as indicated in
table 10-4.
Table 10-4 Synchronization by Writing to FRCs
Clock Source
ø/4
ø/8
ø/32
m, n: Arbitrary integers
After writing these data, synchronization can be checked by reading the three free-running
counters at the same interval as the write interval. If the read data have the same relative
differences as the write data, the three free-running timers are synchronized.
Programs for synchronizing the timers are shown next. Examples a, b, and c can be used when the
program is stored in on-chip memory. Examples d, e, and f can be used when the program is
stored in external memory. These programs assume that no wait states (T
is no NMI input.
Write Interval
4n (states)
8n (states)
32n (states)
Write Data
m
m + n
m + 2n
202
(FRC1)
(FRC2)
(FRC3)
W
) are inserted and there