HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 206

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

To ensure input capture, the pulse width of the input capture signal should be at least 1.5 system
clock periods (1.5·ø).
The ICR is initialized to H'0000 at a reset and in the standby modes.
Note: When input capture is detected, the FRC value is transferred to the ICR even if the input
10.2.4 Timer Control Register (TCR)
Bit
Initial value
Read/Write
The TCR is an 8-bit readable/writable register that selects the FRC clock source, enables the
output compare signals, and enables interrupts.
The TCR is initialized to H'00 at a reset and in the standby modes.
Bit 7—Input Capture Interrupt Enable (ICIE): This bit selects whether to request an input
capture interrupt (ICI) when the input capture flag (ICF) in the timer status/control register
(TCSR) is set to 1.
Bit 7
ICIE
0
1
Bit 6—Output Compare Interrupt Enable B (OCIEB): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in the timer
status/control register (TCSR) is set to 1.
ø
FTI
capture flag (ICF) is already set.
Description
The input capture interrupt request (ICI) is disabled.
The input capture interrupt request (ICI) is enabled.
Minimum FTI Pulse Width
ICIE
R/W
7
0
OCIEB
R/W
6
0
OCIEA
R/W
5
0
OVIE
189
R/W
4
0
OEB
R/W
3
0
(Initial value)
OEA
R/W
2
0
CKS1
R/W
1
0
CKS0
R/W
0
0