HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 196

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

1. Port 9 Data Direction Register (P9DDR)—H'FEFE
Bit
Initial value
Read/Write
P9DDR is an 8-bit register that selects the direction of each pin in port 9. A pin functions as an
output pin if the corresponding bit in P9DDR is set to 1, and as an input pin if the bit is cleared to
0.
P9DDR can be written but not read. An attempt to read this register does not cause an error, but
all bits are read as 1, regardless of their true values.
At a reset and in the hardware standby mode, P9DDR is initialized to H'00, setting all pins for
input. P9DDR is not initialized in the software standby mode, so if a P9DDR bit is set to 1 when
the chip enters the software standby mode, the corresponding pin continues to output the value in
the port 9 data register.
A transition to the software standby mode initializes the on-chip supporting modules, so any pins
of port 9 that were being used by an on-chip module (example: free-running timer output) when
the transition occurs revert to general-purpose input or output, controlled by P9DDR and P9DR.
2. Port 9 Data Register (P9DR)—H'FEFF
Bit
Initial value
Read/Write
P9DR is an 8-bit register containing the data for pins P9
output pins it reads the value in the P9DR latch, but for input pins, it obtains the pin status
directly.
9.10.3 Pin Functions
The pin functions of port 9 are the same in all MCU operating modes. As figure 9-21 indicated,
these pins are used for output of on-chip timer signals and for input and output of serial data and
clock signals as well as for general-purpose input and output. Specifically, they carry output
signals for free-running timers 2 and 3, pulse-width modulation (PWM) timer output signals, and
input and output signals for the serial communication interfaces.
P9
R/W
P9
7
W
7
0
7
0
DDR P9
7
R/W
P9
6
W
6
DDR P9
0
6
0
6
R/W
P9
5
W
5
DDR P9
0
5
0
5
179
R/W
P9
4
W
4
0
4
0
DDR P9
4
7
to P9
R/W
P9
3
W
3
DDR P9
0
3
0
3
0
. When the CPU reads P9DR, for
R/W
P9
2
W
2
0
2
0
DDR P9
2
R/W
P9
1
W
1
DDR P9
0
1
0
1
R/W
P9
0
W
0
DDR
0
0
0
0