HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 134

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

Starting of the DTC is controlled by the six data transfer enable registers, which are located in
high addresses in page 0. Table 6-2 lists these registers.
Table 6-2 Data Transfer Enable Registers
Name
Data transfer enable register A
Data transfer enable register B
Data transfer enable register C
Data transfer enable register D
Data transfer enable register E
Data transfer enable register F
6.2 Register Descriptions
6.2.1 Data Transfer Mode Register (DTMR)
Bit
Read/Write —
The data transfer mode register is a 16-bit register, the first three bits of which designate the data
size and specify whether to increment the source and destination addresses.
Bit 15—Sz (Size): This bit designates the size of the data transferred.
Bit 15
Sz
0
1
* For word transfer, the source and destination addresses must be even addresses.
Bit 14—SI (Source Increment): This bit specifies whether to increment the source address.
Bit 14
SI
0
1
Description
Byte transfer
Word transfer* (two bytes at a time)
Description
Source address is not incremented.
1) If Sz = 0: Source address is incremented by +1 after each data transfer.
2) If Sz = 1: Source address is incremented by +2 after each data transfer.
Sz
15
14
SI
—
13
DI
—
12
—
—
11
—
—
Abbreviation
DTEA
DTEB
DTEC
DTED
DTEE
DTEF
10
—
—
—
—
9
115
—
—
8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
—
—
7
—
—
6
—
—
5
Address
H'FF08
H'FF09
H'FF0A
H'FF0B
H'FF0C
H'FF0D
—
—
4
—
—
3
Initial Value
H'00
H'00
H'00
H'00
H'00
H'00
—
—
2
—
—
1
—
—
0