HD6435348R Hitachi Semiconductor, HD6435348R Datasheet - Page 128

• Manufacturer Part Number: HD6435348R
• Description: Single-Chip Microcomputer
• Manufacturer: Hitachi Semiconductor

5.4.3 Timing of Interrupt Exception-Handling Sequence
Figure 5-4 shows the timing of the exception-handling sequence for an interrupt in minimum
mode when the program area and stack area are both in on-chip memory and the user-coded
interrupt handling routine starts at an even address.
Figure 5-5 shows the timing of the exception-handling sequence for an interrupt in maximum
mode when the program area and stack area are both in external memory.
5.5 Interrupts During Operation of the Data Transfer Controller
If an interrupt is requested during a DTC data transfer cycle, the interrupt is not accepted until the
data transfer cycle has been completed and the next instruction has been executed. This is true
even if the interrupt is an NMI. An example is shown below.
(Example)
Figure 5-3 (b) Stack before and after Interrupt Exception-Handling (Maximum Mode)
Address
2m – 6
2m – 5
2m – 4
2m – 3
2m – 2
2m – 1
2m
Notes:
1. PC: The address of the next instruction to be executed is saved.
2. Register saving and restoring must start at an even address (e.g 2m).
ADD.W
MOV.W
ADD.W
Stack area
(Before)
R2, R0
R0, @H'FE00
@H' FE02,R0
Program flow
SP
Save to stack
DTC interrupt request
109
After data transfer cycle, CPU executes next
instruction before starting exception handling
Data transfer cycle
Fig. 5-3(b)
Address
2m – 6
2m – 5
2m – 4
2m – 3
2m – 2
2m – 1
2m
To NMI exception handling sequence
Upper 8 bits of SR
Lower 8 bits of SR
Upper 8 bits of PC
Lower 8 bits of PC
Don’t care
NMI interrupt
(After)
CP
SP