HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet - Page 56

• Manufacturer Part Number: HYB18M1G320BF
• Description: DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

1) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for -7.5 speed grade.
2) Input slew rate is 1.0 V/ns.
3) Definitions for IDD:
4) All parameters are measured with no output loads.
5) I
Rev.1.00, 2007-03
02022006-J7N7-GYFP
Parameter & Test Conditions
Active power-down standby current with clock stop:
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and
control inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH,
inputs are SWITCHING; data bus inputs are STABLE
Active non power-down standby current with clock stop:
one bank active, CKE is HIGH, CS is HIGH, CK = LOW, CK = HIGH; address and
control inputs are SWITCHING; data bus inputs are STABLE
Operating burst read current:
one bank active; BL = 4; CL = 3;
IOUT = 0 mA; address input are SWITCHING; 50% data change each burst
transfer
Operating burst write current:
one bank active; BL = 4;
address inputs are SWITCHING; 50% data change each burst transfer
Auto-Refresh current:
t
are SWITCHING; data bus inputs are STABLE
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE;
data bus inputs are STABLE
Deep Power Down current
RC
LOW is defined as VIN ≤ 0.1 *
HIGH is defined as VIN ≥ 0.9 *
STABLE is defined as inputs stable at a HIGH or LOW level;
SWITCHING is defined as:
- address and command: inputs changing between HIGH and LOW once per two clock cycles;
- data bus inputs: DQ changing between HIGH and LOW once per clock cycle; DM and DQS are STABLE
DD8
=
t
RFCmin
value shown as typical
;
t
CK
=
t
CKmin
; burst refresh; CKE is HIGH; address and control inputs
t
CK
=
V
t
V
CKmin
DDQ
DDQ
t
CK
;
;
; continuous write bursts;
=
t
CKmin
; continuous read bursts;
t
CK
=
t
CKmin
; address and control
56
I
I
I
I
I
I
I
I
Symbol
DD3PS
DD3N
DD3NS
DD4R
DD4W
DD5
DD6
DD8
3.0
44
5.0
150
150
270
see
Table 27
50
Values
5)
- 7.5
1-Gbit DDR Mobile-RAM
HY[B/E]18M1G320BF
mA
mA
mA
mA
mA
mA
µA
µA
Unit Note
Data Sheet
4)
1)2)3)