HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet - Page 20

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HYB18M1G320BF

Manufacturer Part Number
HYB18M1G320BF
Description
DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM
Manufacturer
QIMONDA [Qimonda AG]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HYB18M1G320BF-7.5
Manufacturer:
LT
Quantity:
95
2.4.4
Before any READ or WRITE commands can be issued to a
bank within the DDR Mobile-RAM, a row in that bank must be
“opened” (activated). This is accomplished via the ACTIVE
command and addresses BA0, BA1, A0 - A12 (see
which decode and select both the bank and the row to be
activated. After opening a row (issuing an ACTIVE
command), a READ or WRITE command may be issued to
that row, subject to the
ACTIVE command to a different row in the same bank can
only be issued after the previous active row has been “closed”
(precharged).
The minimum time interval between successive ACTIVE
commands to the same bank is defined by
ACTIVE command to another bank can be issued while the
first bank is being accessed, which results in a reduction of
total row-access overhead. The minimum time interval
between successive ACTIVE commands to different banks is
defined by
Rev.1.00, 2007-03
02022006-J7N7-GYFP
Command
BA0, BA1
A0-A12
t
RRD
CK
CK
.
ACTIVE
BA x
ACT
Row
t
RCD
specification. A subsequent
NOP
t
RRD
t
RC
. A subsequent
Figure
BA y
ACT
Row
9),
20
NOP
t
RCD
BA0,BA1
NOP
A0-A12
BA = Bank Address
RA = Row Address
CKE
RAS
CAS
WE
CK
CK
CS
RD/WR
BA y
(High)
Col
= Don't Care
Bank Activate Timings
1-Gbit DDR Mobile-RAM
RA
BA
HY[B/E]18M1G320BF
ACTIVE Command
= Don't Care
FIGURE 10
NOP
FIGURE 9
Data Sheet

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