HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet - Page 43

• Manufacturer Part Number: HYB18M1G320BF
• Description: DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.4.10.1
Deep Power-Down mode is a unique feature of DDR Mobile-RAMs for extremely low power consumption. Deep Power-Down
mode is entered using the BURST TERMINATE command (cf
are stopped and all memory data is lost in this mode. To enter the Deep Power-Down mode all banks must be precharged.
The Deep Power-Down mode is asynchronously exited by asserting CKE HIGH. After the exit, the same command sequence
as for power-up initialization, including the 200µs initial pause, has to be applied before any other command may be issued (cf.
Figure
2.4.11
Stopping the clock during idle periods is a very effective method to reduce power consumption. The DDR Mobile-RAM supports
clock stop in case:
• the last access command (ACTIVE, READ, WRITE, PRECHARGE, AUTO REFRESH or MODE REGISTER SET) has
• the related timing condition (
• CKE is held HIGH.
When all conditions have been met, the device is either in “idle” or “row active” state (cf.
be entered with CK held LOW and CK held HIGH.
Clock stop mode is exited by restarting the clock. At least one NOP command has to be issued before the next access
command may be applied. Additional clock pulses might be required depending on the system characteristics.
Figure 38
• initially the device is in clock stop mode;
• the clock is restarted with the rising edge of T0 and a NOP on the command inputs;
• with T1 a valid access command is latched; this command is followed by NOP commands in order to allow for clock stop as
• Tn is the last clock pulse required by the access command latched with T1
• the timing condition of this access command is met with the completion of Tn; therefore Tn is the last clock pulse required
Rev.1.00, 2007-03
02022006-J7N7-GYFP
Parameter
Exit power down delay
CKE minimum low time
executed to completion, including any data-out during read bursts; the number of clock pulses per access command
depends on the device’s AC timing parameters and the clock frequency (see
soon as this access command has completed;
by this command and the clock is then stopped.
4).
illustrates the clock stop mode:
DEEP POWER-DOWN
CLOCK STOP
t
RCD
,
t
WR
,
t
RP
,
t
RFC
,
t
MRD
) has been met;
43
Table
t
t
XP
CKE
Symbol
6) except that CKE is LOW. All internal voltage generators
t
2
CK
Timing Parameters for POWER-DOWN
Table
+ t
min.
IS
16);
- 7.5
Figure
–
–
max.
4), and clock stop mode may
1-Gbit DDR Mobile-RAM
HY[B/E]18M1G320BF
Unit
ns
t
CK
TABLE 15
Data Sheet
Note
–