HYB18M1G320BF QIMONDA [Qimonda AG], HYB18M1G320BF Datasheet - Page 13

• Manufacturer Part Number: HYB18M1G320BF
• Description: DRAMs for Mobile Applications 1-Gbit x32 DDR Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.2.2
The Extended Mode Register controls additional low power features of the device. These include the Partial Array Self Refresh
(PASR), the Temperature Compensated Self Refresh (TCSR) and the drive strength selection for the DQs. The Extended
Mode Register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored
information until it is programmed again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating any subsequent operation. Violating either of these requirements result in unspecified operation. Address bits A0 -
zero. Bits A3 and A4 are “don’t care” (see below).
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Extended Mode Register Definition (BA[1:0] = 10
Rev.1.00, 2007-03
02022006-J7N7-GYFP
Field
DS
TCSR
PASR
A2 specify the Partial Array Self Refresh (PASR) and bits A5 - A6 the Drive Strength, while bits A7 - A12 shall be written to
Bits
[6:5]
[4:3]
[2:0]
Type
w
w
w
Extended Mode Register
Description
Selectable Drive Strength
00
01
10
Note: All other bit combinations are RESERVED.
Temperature Compensated Self Refresh
XX
Partial Array Self Refresh
000
001
010
101
110
Note: All other bit combinations are RESERVED.
B
B
B
B
B
B
B
B
B
DS Full Drive Strength
DS Half Drive Strength
DS Quarter Drive Strength
TCSR Superseded by on-chip temperature sensor (see text)
PASR all banks
PASR half array (BA1 = 0)
PASR quarter array (BA1 = BA0 = 0)
PASR 1/8 array (BA1 = BA0 = RA12 = 0)
PASR 1/16 array (BA1 = BA0 = RA12 = RA11 = 0)
B
)
13
1-Gbit DDR Mobile-RAM
HY[B/E]18M1G320BF
Data Sheet